Searched refs:CTLR_ENABLE_G0_BIT (Results 1 – 5 of 5) sorted by relevance
45 val = CTLR_ENABLE_G0_BIT | FIQ_EN_BIT | FIQ_BYP_DIS_GRP0; in gicv2_cpuif_enable()66 val &= ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT); in gicv2_cpuif_disable()89 if ((ctlr & CTLR_ENABLE_G0_BIT) == 0U) { in gicv2_pcpu_distif_init()91 ctlr | CTLR_ENABLE_G0_BIT); in gicv2_pcpu_distif_init()110 ctlr & ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT)); in gicv2_distif_init()121 gicd_write_ctlr(driver_data->gicd_base, ctlr | CTLR_ENABLE_G0_BIT); in gicv2_distif_init()
48 (CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1S_BIT | in set_gicd_dchipr_rt_owner()83 (CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1S_BIT | in set_gicd_chipr_n()204 (CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1S_BIT | in gic600_multichip_init()
195 ctlr_enable |= CTLR_ENABLE_G0_BIT; in gicv3_secure_spis_config_props()307 ctlr_enable |= CTLR_ENABLE_G0_BIT; in gicv3_secure_ppi_sgi_config_props()
200 CTLR_ENABLE_G0_BIT | in gicv3_distif_init()857 CTLR_ENABLE_G0_BIT | in gicv3_distif_init_restore()
62 #define CTLR_ENABLE_G0_BIT BIT_32(CTLR_ENABLE_G0_SHIFT) macro