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Searched refs:CTLZ_ZERO_UNDEF (Results 1 – 25 of 60) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-ctlz-zero-undef.mir12 ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s32)
13 ; CHECK: $vgpr0 = COPY [[CTLZ_ZERO_UNDEF]](s32)
27 ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s64)
28 ; CHECK: $vgpr0 = COPY [[CTLZ_ZERO_UNDEF]](s32)
42 ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s64)
43 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTLZ_ZERO_UNDEF]](s32)
58 ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s32)
60 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTLZ_ZERO_UNDEF]](s32)
80 ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND]](s32)
82 ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ_ZERO_UNDEF]], [[C1]]
[all …]
Dregbankselect-ctlz-zero-undef.mir14 ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:sgpr(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s32)
15 ; CHECK: S_ENDPGM 0, implicit [[CTLZ_ZERO_UNDEF]](s32)
30 ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:vgpr(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s32)
31 ; CHECK: S_ENDPGM 0, implicit [[CTLZ_ZERO_UNDEF]](s32)
46 ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:sgpr(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s64)
47 ; CHECK: S_ENDPGM 0, implicit [[CTLZ_ZERO_UNDEF]](s32)
65 ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:vgpr(s32) = G_CTLZ_ZERO_UNDEF [[UV]](s32)
67 ; CHECK: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[CTLZ_ZERO_UNDEF]], [[C1]]
Dlegalize-ctlz.mir12 ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s32)
16 ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[CTLZ_ZERO_UNDEF]]
31 ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s64)
35 ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[CTLZ_ZERO_UNDEF]]
50 ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s64)
54 ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[CTLZ_ZERO_UNDEF]]
70 ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s32)
74 ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[CTLZ_ZERO_UNDEF]]
96 ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND]](s32)
100 ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C2]], [[CTLZ_ZERO_UNDEF]]
[all …]
Dlegalize-uitofp.mir78 ; GFX6: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s64)
80 ; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[CTLZ_ZERO_UNDEF]]
84 ; GFX6: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[CTLZ_ZERO_UNDEF]](s32)
107 ; GFX8: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s64)
109 ; GFX8: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[CTLZ_ZERO_UNDEF]]
113 ; GFX8: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[CTLZ_ZERO_UNDEF]](s32)
420 ; GFX6: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND]](s64)
422 ; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ_ZERO_UNDEF]]
426 ; GFX6: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND]], [[CTLZ_ZERO_UNDEF]](s32)
452 ; GFX8: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND]](s64)
[all …]
Dlegalize-sitofp.mir111 ; GFX6: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[XOR]](s64)
113 ; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ_ZERO_UNDEF]]
117 ; GFX6: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[XOR]], [[CTLZ_ZERO_UNDEF]](s32)
151 ; GFX8: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[XOR]](s64)
153 ; GFX8: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ_ZERO_UNDEF]]
157 ; GFX8: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[XOR]], [[CTLZ_ZERO_UNDEF]](s32)
463 ; GFX6: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[XOR]](s64)
465 ; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ_ZERO_UNDEF]]
469 ; GFX6: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[XOR]], [[CTLZ_ZERO_UNDEF]](s32)
505 ; GFX8: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[XOR]](s64)
[all …]
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h345 CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF, enumerator
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h477 CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF, enumerator
/external/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h624 CTLZ_ZERO_UNDEF, enumerator
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp288 case ISD::CTLZ_ZERO_UNDEF: in LegalizeOp()
701 case ISD::CTLZ_ZERO_UNDEF: in Expand()
1032 unsigned Opc = Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF ? ISD::CTLZ : ISD::CTTZ; in ExpandCTLZ_CTTZ_ZERO_UNDEF()
DSelectionDAGDumper.cpp322 case ISD::CTLZ_ZERO_UNDEF: return "ctlz_zero_undef"; in getOperationName()
DLegalizeDAG.cpp2683 case ISD::CTLZ_ZERO_UNDEF: in ExpandBitCount()
2690 if (TLI.isOperationLegalOrCustom(ISD::CTLZ_ZERO_UNDEF, VT)) { in ExpandBitCount()
2692 SDValue CTLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, VT, Op); in ExpandBitCount()
2749 case ISD::CTLZ_ZERO_UNDEF: in ExpandNode()
4013 case ISD::CTLZ_ZERO_UNDEF: in PromoteNode()
4030 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) { in PromoteNode()
DLegalizeIntegerTypes.cpp62 case ISD::CTLZ_ZERO_UNDEF: in PromoteIntegerResult()
1317 case ISD::CTLZ_ZERO_UNDEF: in ExpandIntegerResult()
1970 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi); in ExpandIntRes_CTLZ()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp340 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Custom); in AMDGPUTargetLowering()
346 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); in AMDGPUTargetLowering()
724 case ISD::CTLZ_ZERO_UNDEF: in LowerOperation()
1852 bool ZeroUndef = Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF; in LowerCTLZ()
1870 SDValue CtlzLo = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i32, Lo); in LowerCTLZ()
1871 SDValue CtlzHi = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i32, Hi); in LowerCTLZ()
1943 SDValue LZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i64, L); in LowerINT_TO_FP32()
2474 return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF; in isCtlzOpc()
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp104 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); in BPFTargetLowering()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp393 case ISD::CTLZ_ZERO_UNDEF: in LegalizeOp()
781 case ISD::CTLZ_ZERO_UNDEF: in Expand()
DSelectionDAGDumper.cpp419 case ISD::CTLZ_ZERO_UNDEF: return "ctlz_zero_undef"; in getOperationName()
DLegalizeDAG.cpp2870 case ISD::CTLZ_ZERO_UNDEF: in ExpandNode()
4385 case ISD::CTLZ_ZERO_UNDEF: in ConvertNodeToLibcall()
4445 case ISD::CTLZ_ZERO_UNDEF: in PromoteNode()
4467 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) { in PromoteNode()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFISelLowering.cpp115 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); in BPFTargetLowering()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp399 case ISD::CTLZ_ZERO_UNDEF: return "ctlz_zero_undef"; in getOperationName()
DLegalizeVectorOps.cpp397 case ISD::CTLZ_ZERO_UNDEF: in LegalizeOp()
900 case ISD::CTLZ_ZERO_UNDEF: in Expand()
DLegalizeDAG.cpp2731 case ISD::CTLZ_ZERO_UNDEF: in ExpandNode()
4183 case ISD::CTLZ_ZERO_UNDEF: in ConvertNodeToLibcall()
4241 case ISD::CTLZ_ZERO_UNDEF: in PromoteNode()
4258 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) { in PromoteNode()
/external/llvm-project/llvm/lib/Target/BPF/
DBPFISelLowering.cpp114 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); in BPFTargetLowering()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); in AMDGPUTargetLowering()
1156 case ISD::CTLZ_ZERO_UNDEF: in LowerOperation()
2315 return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF; in isCtlzOpc()
2326 Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF; in LowerCTLZ_CTTZ()
2330 ISDOpc = ISD::CTLZ_ZERO_UNDEF; in LowerCTLZ_CTTZ()
2436 SDValue LZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i64, L); in LowerINT_TO_FP32()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp420 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); in AMDGPUTargetLowering()
1262 case ISD::CTLZ_ZERO_UNDEF: in LowerOperation()
2313 return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF; in isCtlzOpc()
2324 Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF; in LowerCTLZ_CTTZ()
2328 ISDOpc = ISD::CTLZ_ZERO_UNDEF; in LowerCTLZ_CTTZ()
2434 SDValue LZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i64, L); in LowerINT_TO_FP32()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTargetLoweringBase.cpp684 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); in initActions()

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