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Searched refs:CTL_REG (Results 1 – 3 of 3) sorted by relevance

/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/
Ddfs.c111 mr1_val = (mmio_read_32(CTL_REG(0, 133)) >> 16) & 0xffff; in get_dram_drv_odt_val()
129 mr3_val = mmio_read_32(CTL_REG(0, 138)) & 0xf; in get_dram_drv_odt_val()
130 mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0x3; in get_dram_drv_odt_val()
157 mr3_val = (mmio_read_32(CTL_REG(0, 138)) >> 3) & 0x7; in get_dram_drv_odt_val()
158 mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0xff; in get_dram_drv_odt_val()
498 mmio_write_32(CTL_REG(i, 5), tmp); in gen_rk3399_ctl_params_f0()
500 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff, in gen_rk3399_ctl_params_f0()
503 mmio_write_32(CTL_REG(i, 32), in gen_rk3399_ctl_params_f0()
507 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
511 mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1 + in gen_rk3399_ctl_params_f0()
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Dsuspend.c180 mmio_clrsetbits_32(CTL_REG(ch, 200), 0x1 << 8, 0x1 << 8); in override_write_leveling_value()
475 mmio_setbits_32(CTL_REG(i, 276), 1 << 17); in dram_all_config()
500 sram_regcpy(CTL_REG(ch, 1), (uintptr_t)&params_ctl[1], in pctl_cfg()
502 mmio_write_32(CTL_REG(ch, 0), params_ctl[0]); in pctl_cfg()
509 mmio_clrsetbits_32(CTL_REG(ch, 68), PWRUP_SREFRESH_EXIT, in pctl_cfg()
517 mmio_setbits_32(CTL_REG(ch, 0), START); in pctl_cfg()
549 uint32_t fn = ((mmio_read_32(CTL_REG(0, 111)) >> 16) + 1) & 0x1; in dram_switch_to_next_index()
586 mmio_setbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT); in pctl_start()
587 mmio_setbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT); in pctl_start()
606 while (!(mmio_read_32(CTL_REG(0, 203)) & (1 << 3))) { in pctl_start()
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/external/arm-trusted-firmware/plat/rockchip/rk3399/include/shared/
Daddressmap_shared.h92 #define CTL_REG(ch, n) (CTL_BASE(ch) + (n) * 0x4) macro