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Searched refs:CTTZ (Results 1 – 25 of 100) sorted by relevance

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/external/llvm-project/llvm/test/Transforms/SimplifyCFG/AMDGPU/
Dcttz-ctlz.ll68 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
69 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTTZ]]
88 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
89 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTTZ]]
108 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %A, i1 true)
109 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i16 16, i16 [[CTTZ]]
187 ; ALL-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
188 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 63, i64 [[CTTZ]]
207 ; ALL-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
208 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 31, i32 [[CTTZ]]
[all …]
/external/llvm/test/Transforms/SimplifyCFG/AMDGPU/
Dcttz-ctlz.ll68 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
69 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTTZ]]
88 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
89 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTTZ]]
108 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %A, i1 true)
109 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i16 16, i16 [[CTTZ]]
187 ; ALL-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
188 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 63, i64 [[CTTZ]]
207 ; ALL-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
208 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 31, i32 [[CTTZ]]
[all …]
/external/llvm/test/Transforms/InstCombine/
Dffs-1.ll108 ; CHECK-NEXT: [[CTTZ:%[a-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %x, i1 true)
109 ; CHECK-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i32 [[CTTZ]], 1
119 ; CHECK-FFS-NEXT: [[CTTZ:%[a-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %x, i1 true)
120 ; CHECK-FFS-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i32 [[CTTZ]], 1
130 ; CHECK-FFS-NEXT: [[CTTZ:%[a-z0-9]+]] = call i64 @llvm.cttz.i64(i64 %x, i1 true)
131 ; CHECK-FFS-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i64 [[CTTZ]], 1
/external/llvm/test/Transforms/SimplifyCFG/X86/
Dspeculate-cttz-ctlz.ll68 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
69 ; ALL-NEXT: select i1 [[COND]], i64 64, i64 [[CTTZ]]
88 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
89 ; ALL-NEXT: select i1 [[COND]], i32 32, i32 [[CTTZ]]
108 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %A, i1 true)
109 ; ALL-NEXT: select i1 [[COND]], i16 16, i16 [[CTTZ]]
131 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %x, i1 true)
132 ; ALL: [[ZEXT:%[A-Za-z0-9]+]] = zext i32 [[CTTZ]] to i64
154 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %x, i1 true)
155 ; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTTZ]] to i32
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dffs-1.ll151 ; ALL-NEXT: [[CTTZ:%.*]] = call i32 @llvm.cttz.i32(i32 %x, i1 true), !range !0
152 ; ALL-NEXT: [[TMP1:%.*]] = add nuw nsw i32 [[CTTZ]], 1
167 ; TARGET-NEXT: [[CTTZ:%.*]] = call i32 @llvm.cttz.i32(i32 %x, i1 true), !range !0
168 ; TARGET-NEXT: [[TMP1:%.*]] = add nuw nsw i32 [[CTTZ]], 1
183 ; TARGET-NEXT: [[CTTZ:%.*]] = call i64 @llvm.cttz.i64(i64 %x, i1 true), !range !1
184 ; TARGET-NEXT: [[TMP1:%.*]] = trunc i64 [[CTTZ]] to i32
Dadd2.ll332 ; CHECK-NEXT: [[CTTZ:%.*]] = call i16 @llvm.cttz.i16(i16 [[A:%.*]], i1 true), !range !0
333 ; CHECK-NEXT: [[B:%.*]] = or i16 [[CTTZ]], -8
354 ; CHECK-NEXT: [[CTTZ:%.*]] = call i16 @llvm.cttz.i16(i16 [[A:%.*]], i1 true), !range !1
355 ; CHECK-NEXT: [[B:%.*]] = or i16 [[CTTZ]], -16
Dintrinsics.ll287 ; CHECK-NEXT: [[CTTZ:%.*]] = tail call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[OR]], i1 true)
288 ; CHECK-NEXT: ret <2 x i32> [[CTTZ]]
/external/llvm-project/llvm/test/Transforms/SimplifyCFG/PowerPC/
Dcttz-ctlz-spec.ll27 ; CHECK-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
28 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTTZ]]
/external/llvm-project/llvm/test/Transforms/LoopIdiom/X86/
Dcttz.ll4 ; Recognize CTTZ builtin pattern.
47 ; Recognize CTTZ builtin pattern.
/external/llvm-project/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp2323 { ISD::CTTZ, MVT::v8i64, 10 }, in getTypeBasedIntrinsicInstrCost()
2324 { ISD::CTTZ, MVT::v16i32, 14 }, in getTypeBasedIntrinsicInstrCost()
2325 { ISD::CTTZ, MVT::v32i16, 12 }, in getTypeBasedIntrinsicInstrCost()
2326 { ISD::CTTZ, MVT::v64i8, 9 }, in getTypeBasedIntrinsicInstrCost()
2363 { ISD::CTTZ, MVT::v8i64, 20 }, in getTypeBasedIntrinsicInstrCost()
2364 { ISD::CTTZ, MVT::v16i32, 28 }, in getTypeBasedIntrinsicInstrCost()
2365 { ISD::CTTZ, MVT::v32i16, 24 }, in getTypeBasedIntrinsicInstrCost()
2366 { ISD::CTTZ, MVT::v64i8, 18 }, in getTypeBasedIntrinsicInstrCost()
2450 { ISD::CTTZ, MVT::v4i64, 10 }, in getTypeBasedIntrinsicInstrCost()
2451 { ISD::CTTZ, MVT::v8i32, 14 }, in getTypeBasedIntrinsicInstrCost()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp1922 { ISD::CTTZ, MVT::v8i64, 10 }, in getIntrinsicInstrCost()
1923 { ISD::CTTZ, MVT::v16i32, 14 }, in getIntrinsicInstrCost()
1924 { ISD::CTTZ, MVT::v32i16, 12 }, in getIntrinsicInstrCost()
1925 { ISD::CTTZ, MVT::v64i8, 9 }, in getIntrinsicInstrCost()
1942 { ISD::CTTZ, MVT::v8i64, 20 }, in getIntrinsicInstrCost()
1943 { ISD::CTTZ, MVT::v16i32, 28 }, in getIntrinsicInstrCost()
1983 { ISD::CTTZ, MVT::v4i64, 10 }, in getIntrinsicInstrCost()
1984 { ISD::CTTZ, MVT::v8i32, 14 }, in getIntrinsicInstrCost()
1985 { ISD::CTTZ, MVT::v16i16, 12 }, in getIntrinsicInstrCost()
1986 { ISD::CTTZ, MVT::v32i8, 9 }, in getIntrinsicInstrCost()
[all …]
/external/llvm/test/Transforms/SimplifyCFG/PowerPC/
Dcttz-ctlz-spec.ll27 ; CHECK-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h342 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE, enumerator
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h474 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE, enumerator
/external/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h616 CTTZ, enumerator
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp89 setOperationAction(ISD::CTTZ, T, Custom); in initializeHVXLowering()
145 setOperationAction(ISD::CTTZ, T, Custom); in initializeHVXLowering()
1541 case ISD::CTTZ: in LowerHvxOperation()
1573 case ISD::CTTZ: return LowerHvxCttz(Op, DAG); in LowerHvxOperation()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp287 case ISD::CTTZ: in LegalizeOp()
1032 unsigned Opc = Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF ? ISD::CTLZ : ISD::CTTZ; in ExpandCTLZ_CTTZ_ZERO_UNDEF()
DSelectionDAGDumper.cpp319 case ISD::CTTZ: return "cttz"; in getOperationName()
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp101 setOperationAction(ISD::CTTZ, MVT::i64, Custom); in BPFTargetLowering()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp118 setOperationAction(ISD::CTTZ, MVT::i8, Expand); in MSP430TargetLowering()
119 setOperationAction(ISD::CTTZ, MVT::i16, Expand); in MSP430TargetLowering()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp112 setOperationAction(ISD::CTTZ, T, Custom); in initializeHVXLowering()
172 setOperationAction(ISD::CTTZ, T, Custom); in initializeHVXLowering()
2036 case ISD::CTTZ: in LowerHvxOperation()
2073 case ISD::CTTZ: return LowerHvxCttz(Op, DAG); in LowerHvxOperation()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp392 case ISD::CTTZ: in LegalizeOp()
787 case ISD::CTTZ: in Expand()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFISelLowering.cpp112 setOperationAction(ISD::CTTZ, MVT::i64, Custom); in BPFTargetLowering()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp396 case ISD::CTTZ: return "cttz"; in getOperationName()
DLegalizeVectorOps.cpp396 case ISD::CTTZ: in LegalizeOp()
906 case ISD::CTTZ: in Expand()

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