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Searched refs:CTTZ_ZERO_UNDEF (Results 1 – 25 of 57) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-cttz-zero-undef.mir12 ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
13 ; CHECK: $vgpr0 = COPY [[CTTZ_ZERO_UNDEF]](s32)
27 ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s64)
28 ; CHECK: $vgpr0 = COPY [[CTTZ_ZERO_UNDEF]](s32)
42 ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s64)
43 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTTZ_ZERO_UNDEF]](s32)
58 ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
60 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
80 ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[AND]](s32)
81 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
[all …]
Dregbankselect-cttz-zero-undef.mir14 ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:sgpr(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
15 ; CHECK: S_ENDPGM 0, implicit [[CTTZ_ZERO_UNDEF]](s32)
30 ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:vgpr(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
31 ; CHECK: S_ENDPGM 0, implicit [[CTTZ_ZERO_UNDEF]](s32)
46 ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:sgpr(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s64)
47 ; CHECK: S_ENDPGM 0, implicit [[CTTZ_ZERO_UNDEF]](s32)
65 ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:vgpr(s32) = G_CTTZ_ZERO_UNDEF [[UV1]](s32)
67 ; CHECK: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[CTTZ_ZERO_UNDEF]], [[C1]]
Dlegalize-cttz.mir12 ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
16 ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[CTTZ_ZERO_UNDEF]]
31 ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s64)
35 ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[CTTZ_ZERO_UNDEF]]
50 ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s64)
54 ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[CTTZ_ZERO_UNDEF]]
70 ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
74 ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[CTTZ_ZERO_UNDEF]]
98 ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
102 ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C3]], [[CTTZ_ZERO_UNDEF]]
[all …]
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h345 CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF, enumerator
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h477 CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF, enumerator
/external/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h623 CTTZ_ZERO_UNDEF, enumerator
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp289 case ISD::CTTZ_ZERO_UNDEF: in LegalizeOp()
702 case ISD::CTTZ_ZERO_UNDEF: in Expand()
DSelectionDAGDumper.cpp320 case ISD::CTTZ_ZERO_UNDEF: return "cttz_zero_undef"; in getOperationName()
DLegalizeIntegerTypes.cpp65 case ISD::CTTZ_ZERO_UNDEF: in PromoteIntegerResult()
1320 case ISD::CTTZ_ZERO_UNDEF: in ExpandIntegerResult()
2000 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo); in ExpandIntRes_CTTZ()
DLegalizeDAG.cpp2717 case ISD::CTTZ_ZERO_UNDEF: in ExpandBitCount()
2751 case ISD::CTTZ_ZERO_UNDEF: in ExpandNode()
4011 case ISD::CTTZ_ZERO_UNDEF: in PromoteNode()
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp103 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom); in BPFTargetLowering()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp394 case ISD::CTTZ_ZERO_UNDEF: in LegalizeOp()
788 case ISD::CTTZ_ZERO_UNDEF: in Expand()
DSelectionDAGDumper.cpp417 case ISD::CTTZ_ZERO_UNDEF: return "cttz_zero_undef"; in getOperationName()
DLegalizeDAG.cpp2875 case ISD::CTTZ_ZERO_UNDEF: in ExpandNode()
4443 case ISD::CTTZ_ZERO_UNDEF: in PromoteNode()
4449 Node->getOpcode() == ISD::CTTZ_ZERO_UNDEF) in PromoteNode()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFISelLowering.cpp114 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom); in BPFTargetLowering()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp397 case ISD::CTTZ_ZERO_UNDEF: return "cttz_zero_undef"; in getOperationName()
DLegalizeVectorOps.cpp398 case ISD::CTTZ_ZERO_UNDEF: in LegalizeOp()
907 case ISD::CTTZ_ZERO_UNDEF: in Expand()
DLegalizeIntegerTypes.cpp66 case ISD::CTTZ_ZERO_UNDEF: in PromoteIntegerResult()
1812 case ISD::CTTZ_ZERO_UNDEF: in ExpandIntegerResult()
2658 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo); in ExpandIntRes_CTTZ()
/external/llvm-project/llvm/lib/Target/BPF/
DBPFISelLowering.cpp113 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom); in BPFTargetLowering()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp352 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom); in AMDGPUTargetLowering()
1154 case ISD::CTTZ_ZERO_UNDEF: in LowerOperation()
2319 return Opc == ISD::CTTZ || Opc == ISD::CTTZ_ZERO_UNDEF; in isCttzOpc()
2325 bool ZeroUndef = Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF || in LowerCTLZ_CTTZ()
2333 ISDOpc = ISD::CTTZ_ZERO_UNDEF; in LowerCTLZ_CTTZ()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp418 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom); in AMDGPUTargetLowering()
1260 case ISD::CTTZ_ZERO_UNDEF: in LowerOperation()
2317 return Opc == ISD::CTTZ || Opc == ISD::CTTZ_ZERO_UNDEF; in isCttzOpc()
2323 bool ZeroUndef = Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF || in LowerCTLZ_CTTZ()
2331 ISDOpc = ISD::CTTZ_ZERO_UNDEF; in LowerCTLZ_CTTZ()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp599 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom); in ARMTargetLowering()
600 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom); in ARMTargetLowering()
601 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom); in ARMTargetLowering()
602 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom); in ARMTargetLowering()
604 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom); in ARMTargetLowering()
605 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom); in ARMTargetLowering()
606 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom); in ARMTargetLowering()
607 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom); in ARMTargetLowering()
4626 (N->getOpcode() == ISD::CTTZ_ZERO_UNDEF)) { in LowerCTTZ()
7186 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op.getNode(), DAG, Subtarget); in LowerOperation()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTargetLoweringBase.cpp685 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); in initActions()
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp888 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); in initActions()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMISelLowering.cpp899 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom); in ARMTargetLowering()
900 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom); in ARMTargetLowering()
901 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom); in ARMTargetLowering()
902 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom); in ARMTargetLowering()
904 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom); in ARMTargetLowering()
905 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom); in ARMTargetLowering()
906 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom); in ARMTargetLowering()
907 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom); in ARMTargetLowering()
5967 (N->getOpcode() == ISD::CTTZ_ZERO_UNDEF)) { in LowerCTTZ()
9330 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op.getNode(), DAG, Subtarget); in LowerOperation()

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