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Searched refs:CTX_EL3STATE_OFFSET (Results 1 – 5 of 5) sorted by relevance

/external/arm-trusted-firmware/bl31/aarch64/
Dea_delegate.S239 ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3]
247 stp x2, x3, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
255 stp x4, x5, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
271 ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
297 ldp x1, x2, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
302 ldp x3, x4, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
312 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_ESR_EL3]
Druntime_exceptions.S102 str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
141 str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
155 ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
223 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
226 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
487 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
500 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
501 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
/external/arm-trusted-firmware/bl1/aarch64/
Dbl1_exceptions.S166 ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
256 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
273 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
274 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
/external/arm-trusted-firmware/include/lib/el3_runtime/aarch64/
Dcontext.h56 #define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) macro
72 #define CTX_EL1_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END)
470 CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), \
/external/arm-trusted-firmware/lib/el3_runtime/aarch64/
Dcontext.S784 str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
869 ldr x0, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
956 str x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
962 ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
963 ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
1002 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]