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Searched refs:CalleeSavedRegs (Results 1 – 25 of 64) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCCallingConv.td283 def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27,
286 def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
293 def CSR_Darwin32_Altivec : CalleeSavedRegs<(add CSR_Darwin32, CSR_Altivec)>;
296 def CSR_SVR432_COMM : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
300 def CSR_SVR432 : CalleeSavedRegs<(add CSR_SVR432_COMM, F14, F15, F16, F17, F18,
304 def CSR_SPE : CalleeSavedRegs<(add S14, S15, S16, S17, S18, S19, S20, S21, S22,
308 def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
310 def CSR_SVR432_SPE : CalleeSavedRegs<(add CSR_SVR432_COMM, CSR_SPE)>;
312 def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
319 def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20,
[all …]
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVCallingConv.td17 : CalleeSavedRegs<(add X1, X3, X4, X8, X9, (sequence "X%u", 18, 27))>;
20 : CalleeSavedRegs<(add CSR_ILP32_LP64,
24 : CalleeSavedRegs<(add CSR_ILP32_LP64,
28 def CSR_NoRegs : CalleeSavedRegs<(add)>;
32 def CSR_Interrupt : CalleeSavedRegs<(add X1,
40 def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add X1,
54 def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add X1,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVCallingConv.td17 : CalleeSavedRegs<(add X1, X3, X4, X8, X9, (sequence "X%u", 18, 27))>;
20 : CalleeSavedRegs<(add CSR_ILP32_LP64,
24 : CalleeSavedRegs<(add CSR_ILP32_LP64,
28 def CSR_NoRegs : CalleeSavedRegs<(add)>;
32 def CSR_Interrupt : CalleeSavedRegs<(add X1,
40 def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add X1,
54 def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add X1,
/external/llvm/lib/Target/PowerPC/
DPPCCallingConv.td219 def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27,
222 def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
229 def CSR_Darwin32_Altivec : CalleeSavedRegs<(add CSR_Darwin32, CSR_Altivec)>;
231 def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
238 def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
240 def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20,
247 def CSR_Darwin64_Altivec : CalleeSavedRegs<(add CSR_Darwin64, CSR_Altivec)>;
249 def CSR_SVR464 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,
257 def CSR_SRV464_TLS_PE : CalleeSavedRegs<(add)>;
259 def CSR_SVR464_ViaCopy : CalleeSavedRegs<(add CSR_SVR464)>;
[all …]
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCCallingConv.td267 def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27,
271 def CSR_SVR432_COMM : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
275 def CSR_SVR432 : CalleeSavedRegs<(add CSR_SVR432_COMM, F14, F15, F16, F17, F18,
279 def CSR_SPE : CalleeSavedRegs<(add S14, S15, S16, S17, S18, S19, S20, S21, S22,
283 def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
285 def CSR_SVR432_SPE : CalleeSavedRegs<(add CSR_SVR432_COMM, CSR_SPE)>;
287 def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
294 def CSR_AIX32_Altivec : CalleeSavedRegs<(add CSR_AIX32, CSR_Altivec)>;
296 // Common CalleeSavedRegs for SVR4 and AIX.
297 def CSR_PPC64 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64CallingConvention.td379 def CSR_AArch64_AAPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24,
386 def CSR_AArch64_AAPCS_X18 : CalleeSavedRegs<(add X18, CSR_AArch64_AAPCS)>;
391 def CSR_Win_AArch64_AAPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24,
398 def CSR_Win_AArch64_CFGuard_Check : CalleeSavedRegs<(add CSR_Win_AArch64_AAPCS,
404 def CSR_AArch64_AAVPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24,
410 def CSR_AArch64_SVE_AAPCS : CalleeSavedRegs<(add (sequence "Z%u", 8, 23),
423 def CSR_AArch64_AAPCS_ThisReturn : CalleeSavedRegs<(add CSR_AArch64_AAPCS, X0)>;
426 : CalleeSavedRegs<(sub CSR_AArch64_AAPCS, X21)>;
431 : CalleeSavedRegs<(add (sequence "X%u", 1, 28), FP,
435 : CalleeSavedRegs<(add (sequence "W%u", 0, 30), WSP,
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallingConv.td263 def CSR_NoRegs : CalleeSavedRegs<(add)>;
264 def CSR_FPRegs : CalleeSavedRegs<(add (sequence "D%u", 0, 31))>;
266 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
271 def CSR_Win_AAPCS_CFGuard_Check : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7,
275 def CSR_AAPCS_SwiftError : CalleeSavedRegs<(sub CSR_AAPCS, R8)>;
281 def CSR_AAPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
286 def CSR_AAPCS_SplitPush_SwiftError : CalleeSavedRegs<(sub CSR_AAPCS_SplitPush,
293 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
299 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
302 def CSR_iOS_SwiftError : CalleeSavedRegs<(sub CSR_iOS, R8)>;
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMCallingConv.td267 def CSR_NoRegs : CalleeSavedRegs<(add)>;
268 def CSR_FPRegs : CalleeSavedRegs<(add (sequence "D%u", 0, 31))>;
270 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
275 def CSR_Win_AAPCS_CFGuard_Check : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7,
279 def CSR_AAPCS_SwiftError : CalleeSavedRegs<(sub CSR_AAPCS, R8)>;
285 def CSR_AAPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
290 def CSR_AAPCS_SplitPush_SwiftError : CalleeSavedRegs<(sub CSR_AAPCS_SplitPush,
297 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
303 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
306 def CSR_iOS_SwiftError : CalleeSavedRegs<(sub CSR_iOS, R8)>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CallingConvention.td375 def CSR_AArch64_AAPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24,
381 def CSR_Darwin_AArch64_AAPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21, X22,
389 def CSR_Win_AArch64_AAPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24,
396 def CSR_Win_AArch64_CFGuard_Check : CalleeSavedRegs<(add CSR_Win_AArch64_AAPCS,
402 def CSR_AArch64_AAVPCS : CalleeSavedRegs<(add X19, X20, X21, X22, X23, X24,
408 def CSR_AArch64_SVE_AAPCS : CalleeSavedRegs<(add (sequence "Z%u", 8, 23),
421 def CSR_AArch64_AAPCS_ThisReturn : CalleeSavedRegs<(add CSR_AArch64_AAPCS, X0)>;
424 : CalleeSavedRegs<(sub CSR_Darwin_AArch64_AAPCS, X21)>;
431 : CalleeSavedRegs<(add (sub (sequence "X%u", 1, 28), X16, X17),
440 : CalleeSavedRegs<(add CSR_Darwin_AArch64_AAPCS,
[all …]
/external/llvm/lib/Target/ARM/
DARMCallingConv.td244 def CSR_NoRegs : CalleeSavedRegs<(add)>;
246 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
253 def CSR_AAPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
261 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
267 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
270 def CSR_iOS_SwiftError : CalleeSavedRegs<(sub CSR_iOS, R6)>;
272 def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
275 def CSR_iOS_TLSCall : CalleeSavedRegs<(add LR, SP,
281 def CSR_iOS_CXX_TLS : CalleeSavedRegs<(add CSR_iOS, (sequence "R%u", 12, 1),
285 def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallingConv.td1067 def CSR_NoRegs : CalleeSavedRegs<(add)>;
1069 def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>;
1070 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
1072 def CSR_64_SwiftError : CalleeSavedRegs<(sub CSR_64, R12)>;
1074 def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>;
1075 def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>;
1077 def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>;
1079 def CSR_Win64 : CalleeSavedRegs<(add CSR_Win64_NoSSE,
1082 def CSR_Win64_SwiftError : CalleeSavedRegs<(sub CSR_Win64, R12)>;
1087 def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI,
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86CallingConv.td1074 def CSR_NoRegs : CalleeSavedRegs<(add)>;
1076 def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>;
1077 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
1079 def CSR_64_SwiftError : CalleeSavedRegs<(sub CSR_64, R12)>;
1081 def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>;
1082 def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>;
1084 def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>;
1086 def CSR_Win64 : CalleeSavedRegs<(add CSR_Win64_NoSSE,
1089 def CSR_Win64_SwiftError : CalleeSavedRegs<(sub CSR_Win64, R12)>;
1094 def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI,
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/VE/
DVECallingConv.td18 def CSR : CalleeSavedRegs<(add (sequence "SX%u", 18, 33))>;
19 def CSR_NoRegs : CalleeSavedRegs<(add)>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUCallingConv.td84 def CSR_AMDGPU_VGPRs_24_255 : CalleeSavedRegs<
88 def CSR_AMDGPU_VGPRs_32_255 : CalleeSavedRegs<
92 def CSR_AMDGPU_SGPRs_32_105 : CalleeSavedRegs<
97 def CSR_AMDGPU_AllVGPRs : CalleeSavedRegs<
102 def CSR_AMDGPU_AllAllocatableSRegs : CalleeSavedRegs<
106 def CSR_AMDGPU_HighRegs : CalleeSavedRegs<
/external/llvm/lib/Target/X86/
DX86CallingConv.td853 def CSR_NoRegs : CalleeSavedRegs<(add)>;
855 def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>;
856 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
858 def CSR_64_SwiftError : CalleeSavedRegs<(sub CSR_64, R12)>;
860 def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>;
861 def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>;
863 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
869 def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI,
873 def CSR_64_CXX_TLS_Darwin_PE : CalleeSavedRegs<(add RBP)>;
876 def CSR_64_CXX_TLS_Darwin_ViaCopy : CalleeSavedRegs<(sub CSR_64_TLS_Darwin, RBP)>;
[all …]
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUCallingConv.td152 def CSR_AMDGPU_VGPRs_24_255 : CalleeSavedRegs<
156 def CSR_AMDGPU_VGPRs_32_255 : CalleeSavedRegs<
160 def CSR_AMDGPU_VGPRs : CalleeSavedRegs<
178 def CSR_AMDGPU_SGPRs_32_105 : CalleeSavedRegs<
183 def CSR_AMDGPU_AllVGPRs : CalleeSavedRegs<
188 def CSR_AMDGPU_AllAllocatableSRegs : CalleeSavedRegs<
192 def CSR_AMDGPU_HighRegs : CalleeSavedRegs<
196 def CSR_AMDGPU_NoRegs : CalleeSavedRegs<(add)>;
/external/llvm-project/llvm/lib/Target/Mips/
DMipsCallingConv.td362 def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP,
365 def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
370 def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
374 CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP,
377 def CSR_N32 : CalleeSavedRegs<(add D20_64, D22_64, D24_64, D26_64, D28_64,
381 def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
385 CalleeSavedRegs<(add V0, V1, FP,
389 def CSR_Interrupt_32R6 : CalleeSavedRegs<(add (sequence "A%u", 3, 0),
395 def CSR_Interrupt_32 : CalleeSavedRegs<(add (sequence "A%u", 3, 0),
401 def CSR_Interrupt_64R6 : CalleeSavedRegs<(add (sequence "A%u_64", 3, 0),
[all …]
/external/llvm/lib/Target/Mips/
DMipsCallingConv.td356 def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP,
359 def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
364 def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
368 CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP,
371 def CSR_N32 : CalleeSavedRegs<(add D20_64, D22_64, D24_64, D26_64, D28_64,
375 def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
379 CalleeSavedRegs<(add V0, V1, FP,
383 def CSR_Interrupt_32R6 : CalleeSavedRegs<(add (sequence "A%u", 3, 0),
389 def CSR_Interrupt_32 : CalleeSavedRegs<(add (sequence "A%u", 3, 0),
395 def CSR_Interrupt_64R6 : CalleeSavedRegs<(add (sequence "A%u_64", 3, 0),
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsCallingConv.td362 def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP,
365 def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
370 def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
374 CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP,
377 def CSR_N32 : CalleeSavedRegs<(add D20_64, D22_64, D24_64, D26_64, D28_64,
381 def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
385 CalleeSavedRegs<(add V0, V1, FP,
389 def CSR_Interrupt_32R6 : CalleeSavedRegs<(add (sequence "A%u", 3, 0),
395 def CSR_Interrupt_32 : CalleeSavedRegs<(add (sequence "A%u", 3, 0),
401 def CSR_Interrupt_64R6 : CalleeSavedRegs<(add (sequence "A%u_64", 3, 0),
[all …]
/external/llvm/lib/Target/NVPTX/
DNVPTXRegisterInfo.cpp82 static const MCPhysReg CalleeSavedRegs[] = { 0 }; in getCalleeSavedRegs() local
83 return CalleeSavedRegs; in getCalleeSavedRegs()
/external/llvm-project/llvm/lib/Target/AVR/
DAVRCallingConv.td40 def CSR_Normal : CalleeSavedRegs<(add R29, R28, (sequence "R%u", 17, 2))>;
41 def CSR_Interrupts : CalleeSavedRegs<(add (sequence "R%u", 31, 0))>;
/external/llvm-project/llvm/lib/Target/NVPTX/
DNVPTXRegisterInfo.cpp103 static const MCPhysReg CalleeSavedRegs[] = { 0 }; in getCalleeSavedRegs() local
104 return CalleeSavedRegs; in getCalleeSavedRegs()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXRegisterInfo.cpp103 static const MCPhysReg CalleeSavedRegs[] = { 0 }; in getCalleeSavedRegs() local
104 return CalleeSavedRegs; in getCalleeSavedRegs()
/external/llvm/lib/Target/AArch64/
DAArch64CallingConvention.td269 def CSR_AArch64_AAPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21, X22,
282 def CSR_AArch64_AAPCS_ThisReturn : CalleeSavedRegs<(add CSR_AArch64_AAPCS, X0)>;
285 : CalleeSavedRegs<(sub CSR_AArch64_AAPCS, X19)>;
292 : CalleeSavedRegs<(add (sub (sequence "X%u", 1, 28), X16, X17),
301 : CalleeSavedRegs<(add CSR_AArch64_AAPCS,
307 : CalleeSavedRegs<(add LR, FP)>;
311 : CalleeSavedRegs<(sub CSR_AArch64_CXX_TLS_Darwin, LR, FP)>;
316 : CalleeSavedRegs<(add (sequence "X%u", 1, 28), FP,
320 : CalleeSavedRegs<(add (sequence "W%u", 0, 30), WSP,
326 def CSR_AArch64_NoRegs : CalleeSavedRegs<(add)>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRCallingConv.td56 def CSR_Normal : CalleeSavedRegs<(add R29, R28, (sequence "R%u", 17, 2))>;
57 def CSR_Interrupts : CalleeSavedRegs<(add (sequence "R%u", 31, 0))>;

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