| /external/tensorflow/tensorflow/compiler/mlir/lite/tests/end2end/ |
| D | graph_with_placeholder_with_default.pbtxt | 30 name: "tf.Const1"
55 input: "tf.Const1"
82 input: "tf.Const1"
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| /external/tensorflow/tensorflow/compiler/mlir/tensorflow/tests/mlir2graphdef/ |
| D | tf_identity_n.mlir | 6 …and wraps "tf.Const"() {value = dense<4.2> : tensor<4x5xf32>} : () -> tensor<4x5xf32> loc("Const1")
16 // CHECK-NEXT: input: "Const1"
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| D | parse_example.mlir | 7 // CHECK-NEXT: input: "tf.Const1"
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| D | parse_example_v2.mlir | 23 // CHECK-NEXT: input: "tf.Const1"
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | f16-imm.ll | 26 define half @Const1() {
27 ; CHECK-FP16-LABEL: Const1:
32 ; CHECK-NOFP16-LABEL: Const1:
|
| /external/rust/crates/pin-project/tests/ui/pinned_drop/ |
| D | invalid.rs | 85 struct Const1(()); struct
88 impl PinnedDrop for Const1 { implementation
|
| /external/tensorflow/tensorflow/compiler/mlir/lite/tests/mlir2flatbuffer/ |
| D | logical.mlir | 29 // CHECK-NEXT: name: "Const1",
94 %0 = "tfl.pseudo_const" () {value = dense<true> : tensor<4xi1>} : () -> tensor<4xi1> loc("Const1")
|
| D | tfl_while_op.mlir | 125 // CHECK-NEXT: name: "Const1",
212 %cst = constant dense<1> : tensor<i32> loc("Const1")
|
| D | while_op.mlir | 125 // CHECK-NEXT: name: "Const1",
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| D | lstm.mlir | 175 // CHECK-NEXT: name: "Const1",
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| D | unidirectional_sequence_lstm.mlir | 175 // CHECK-NEXT: name: "Const1",
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceGlobalContext.cpp | 93 bool operator()(const Constant *Const1, const Constant *Const2) const { in operator ()()
97 typename ValueType::PrimType V1 = llvm::cast<ValueType>(Const1)->getValue(); in operator ()()
113 bool operator()(const Constant *Const1, const Constant *Const2) const { in operator ()()
114 typename ValueType::PrimType V1 = llvm::cast<ValueType>(Const1)->getValue(); in operator ()()
123 bool operator()(const Constant *Const1, const Constant *Const2) const { in operator ()()
124 auto *V1 = llvm::cast<ValueType>(Const1); in operator ()()
|
| D | IceTargetLoweringMIPS32.cpp | 5301 auto *Const1 = llvm::dyn_cast<ConstantInteger32>(Src1); in matchOffsetBase() local
5310 if (Var1 == nullptr && Const1 == nullptr) { in matchOffsetBase()
5331 if (Const1) { in matchOffsetBase()
5332 int32_t MoreOffset = IsAdd ? Const1->getValue() : -Const1->getValue(); in matchOffsetBase()
|
| D | IceTargetLoweringX86BaseImpl.h | 5705 auto *Const1 = llvm::dyn_cast<ConstantInteger32>(Src1);
5713 if (Var0 && Const1) {
5715 Const = Const1;
5788 if (Const1) {
5790 IsAdd ? Const1->getValue() : -Const1->getValue();
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| D | IceTargetLoweringARM32.cpp | 5713 auto *Const1 = llvm::dyn_cast<ConstantInteger32>(Src1); in matchOffsetBase() local
5722 if (Var1 == nullptr && Const1 == nullptr) { in matchOffsetBase()
5743 if (Const1) { in matchOffsetBase()
5744 int32_t MoreOffset = IsAdd ? Const1->getValue() : -Const1->getValue(); in matchOffsetBase()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 941 SDValue Const1; in performORCombine() local
944 Const1 = DAG.getConstant(SMPos0, DL, MVT::i32); in performORCombine()
945 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); in performORCombine()
2325 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); in lowerFCOPYSIGN32() local
2334 Const1); in lowerFCOPYSIGN32()
2338 Const1); in lowerFCOPYSIGN32()
2343 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); in lowerFCOPYSIGN32()
2344 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); in lowerFCOPYSIGN32()
2351 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); in lowerFCOPYSIGN32()
2352 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in lowerFCOPYSIGN32()
[all …]
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 942 SDValue Const1; in performORCombine() local
945 Const1 = DAG.getConstant(SMPos0, DL, MVT::i32); in performORCombine()
946 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); in performORCombine()
2323 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); in lowerFCOPYSIGN32() local
2332 Const1); in lowerFCOPYSIGN32()
2336 Const1); in lowerFCOPYSIGN32()
2341 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); in lowerFCOPYSIGN32()
2342 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); in lowerFCOPYSIGN32()
2349 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); in lowerFCOPYSIGN32()
2350 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in lowerFCOPYSIGN32()
[all …]
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 2000 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); in lowerFCOPYSIGN32() local
2009 Const1); in lowerFCOPYSIGN32()
2013 Const1); in lowerFCOPYSIGN32()
2018 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); in lowerFCOPYSIGN32()
2019 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); in lowerFCOPYSIGN32()
2026 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); in lowerFCOPYSIGN32()
2027 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in lowerFCOPYSIGN32()
2048 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); in lowerFCOPYSIGN64() local
2058 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1); in lowerFCOPYSIGN64()
2066 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1, in lowerFCOPYSIGN64()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 1419 auto Const1 = B.buildConstant(S32, ExpBits); in extractF64Exponent() local
1423 .addUse(Const1.getReg(0)); in extractF64Exponent()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | CodeGenPrepare.cpp | 7644 bool Const1 = isa<ConstantInt>(Op1) || isa<ConstantFP>(Op1) || in optimizeInst() local
7646 if (Const0 || Const1) { in optimizeInst()
7647 if (!Const0 || !Const1) { in optimizeInst()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 1940 auto Const1 = B.buildConstant(S32, ExpBits); in extractF64Exponent() local
1945 .addUse(Const1.getReg(0)); in extractF64Exponent()
|
| /external/tensorflow/tensorflow/compiler/mlir/lite/tests/ |
| D | ops.mlir | 2450 %cst = constant dense<1> : tensor<i32> loc("Const1")
|