| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | callbr-asm-bb-exports.ll | 9 ; CHECK-NEXT: t4: i32,ch = CopyFromReg t0, Register:i32 %3
12 ; CHECK-NEXT: t6: i32,ch = CopyFromReg t0, Register:i32 %4
16 ; CHECK-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %2
|
| D | merge-store-partially-alias-loads.ll | 18 ; DBGDAG-DAG: [[BASEPTR:t[0-9]+]]: i64,ch = CopyFromReg [[ENTRYTOKEN]],
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 84 case ISD::CopyFromReg: NumberDeps++; break; in numberRCValPredInSU()
121 case ISD::CopyFromReg: break; in numberRCValSuccInSU()
444 case ISD::CopyFromReg: in SUSchedulingCost()
549 case ISD::CopyFromReg: in initNumRegDefsLeft()
|
| D | StatepointLowering.cpp | 342 while (CallEnd->getOpcode() == ISD::CopyFromReg) in lowerCallFromStatepointLoweringInfo()
982 SDValue CopyFromReg = getCopyFromRegs(I, RetTy); in visitGCResult() local
984 assert(CopyFromReg.getNode()); in visitGCResult()
985 setValue(&CI, CopyFromReg); in visitGCResult()
|
| D | ScheduleDAGRRList.cpp | 323 if (!Node->isMachineOpcode() && Node->getOpcode() == ISD::CopyFromReg) { in GetCostForDef()
711 case ISD::CopyFromReg: in EmitNode()
1279 if (N->getOpcode() == ISD::CopyFromReg) { in getPhysicalRegisterVT()
2271 if (PN->getOpcode() == ISD::CopyFromReg) { in unscheduledNode()
2362 PredSU->getNode()->getOpcode() == ISD::CopyFromReg) { in hasOnlyLiveInOpers()
2433 assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg && in resetVRegCycle()
2450 Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) { in hasVRegCycleUse()
3001 if (N->getOpcode() == ISD::CopyFromReg && in PrescheduleNodesWithMultipleUses()
|
| D | InstrEmitter.cpp | 341 Op.getNode()->getOpcode() != ISD::CopyFromReg && in AddRegisterOperand()
947 if (F->getOpcode() == ISD::CopyFromReg) { in EmitMachineNode()
1018 case ISD::CopyFromReg: { in EmitSpecialNode()
|
| D | ScheduleDAGSDNodes.cpp | 122 if (Def->getOpcode() == ISD::CopyFromReg && in CheckForPhysRegDependency()
547 if (Node->getOpcode() == ISD::CopyFromReg) in InitNodeNumDefs()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 88 case ISD::CopyFromReg: NumberDeps++; break; in numberRCValPredInSU()
125 case ISD::CopyFromReg: break; in numberRCValSuccInSU()
448 case ISD::CopyFromReg: in SUSchedulingCost()
553 case ISD::CopyFromReg: in initNumRegDefsLeft()
|
| D | StatepointLowering.cpp | 339 while (CallEnd->getOpcode() == ISD::CopyFromReg) in lowerCallFromStatepointLoweringInfo()
1125 SDValue CopyFromReg = getCopyFromRegs(SI, RetTy); in visitGCResult() local
1127 assert(CopyFromReg.getNode()); in visitGCResult()
1128 setValue(&CI, CopyFromReg); in visitGCResult()
|
| D | ScheduleDAGRRList.cpp | 323 if (!Node->isMachineOpcode() && Node->getOpcode() == ISD::CopyFromReg) { in GetCostForDef()
711 case ISD::CopyFromReg: in EmitNode()
1279 if (N->getOpcode() == ISD::CopyFromReg) { in getPhysicalRegisterVT()
2274 if (PN->getOpcode() == ISD::CopyFromReg) { in unscheduledNode()
2365 PredSU->getNode()->getOpcode() == ISD::CopyFromReg) { in hasOnlyLiveInOpers()
2436 assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg && in resetVRegCycle()
2453 Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) { in hasVRegCycleUse()
3004 if (N->getOpcode() == ISD::CopyFromReg && in PrescheduleNodesWithMultipleUses()
|
| D | InstrEmitter.cpp | 349 Op.getNode()->getOpcode() != ISD::CopyFromReg && in AddRegisterOperand()
1014 if (F->getOpcode() == ISD::CopyFromReg) { in EmitMachineNode()
1101 case ISD::CopyFromReg: { in EmitSpecialNode()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 88 case ISD::CopyFromReg: NumberDeps++; break; in numberRCValPredInSU()
125 case ISD::CopyFromReg: break; in numberRCValSuccInSU()
456 case ISD::CopyFromReg: in SUSchedulingCost()
562 case ISD::CopyFromReg: in initNumRegDefsLeft()
|
| D | StatepointLowering.cpp | 316 while (CallEnd->getOpcode() == ISD::CopyFromReg) in lowerCallFromStatepointLoweringInfo()
881 SDValue CopyFromReg = getCopyFromRegs(I, RetTy); in visitGCResult() local
883 assert(CopyFromReg.getNode()); in visitGCResult()
884 setValue(&CI, CopyFromReg); in visitGCResult()
|
| D | ScheduleDAGRRList.cpp | 289 if (!Node->isMachineOpcode() && Node->getOpcode() == ISD::CopyFromReg) { in GetCostForDef()
682 case ISD::CopyFromReg: in EmitNode()
1192 if (N->getOpcode() == ISD::CopyFromReg) { in getPhysicalRegisterVT()
2129 if (PN->getOpcode() == ISD::CopyFromReg) { in unscheduledNode()
2220 PredSU->getNode()->getOpcode() == ISD::CopyFromReg) { in hasOnlyLiveInOpers()
2291 assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg && in resetVRegCycle()
2308 Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) { in hasVRegCycleUse()
2835 if (N->getOpcode() == ISD::CopyFromReg && in PrescheduleNodesWithMultipleUses()
|
| D | InstrEmitter.cpp | 354 Op.getNode()->getOpcode() != ISD::CopyFromReg && in AddRegisterOperand()
850 if (F->getOpcode() == ISD::CopyFromReg) { in EmitMachineNode()
913 case ISD::CopyFromReg: { in EmitSpecialNode()
|
| D | ScheduleDAGSDNodes.cpp | 122 if (Def->getOpcode() == ISD::CopyFromReg && in CheckForPhysRegDependency()
530 if (Node->getOpcode() == ISD::CopyFromReg) in InitNodeNumDefs()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRISelDAGToDAG.cpp | 250 if (CopyFromRegOp->getOpcode() == ISD::CopyFromReg) { in SelectInlineAsmMemoryOperand()
300 SDValue CopyFromReg = in SelectInlineAsmMemoryOperand() local
303 OutOps.push_back(CopyFromReg); in SelectInlineAsmMemoryOperand()
|
| /external/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRISelDAGToDAG.cpp | 247 if (CopyFromRegOp->getOpcode() == ISD::CopyFromReg) { in SelectInlineAsmMemoryOperand()
297 SDValue CopyFromReg = in SelectInlineAsmMemoryOperand() local
300 OutOps.push_back(CopyFromReg); in SelectInlineAsmMemoryOperand()
|
| /external/llvm/test/CodeGen/X86/ |
| D | merge-store-partially-alias-loads.ll | 18 ; DBGDAG-DAG: [[BASEPTR:t[0-9]+]]: i64,ch = CopyFromReg [[ENTRYTOKEN]],
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 170 CopyFromReg, enumerator
|
| /external/llvm/lib/Target/X86/ |
| D | README-X86-64.txt | 46 emits a CopyFromReg which gets turned into a movb and that can be allocated a
49 To get around this, isel emits a CopyFromReg from AX and then right shift it
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | README-X86-64.txt | 46 emits a CopyFromReg which gets turned into a movb and that can be allocated a
49 To get around this, isel emits a CopyFromReg from AX and then right shift it
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | README-X86-64.txt | 46 emits a CopyFromReg which gets turned into a movb and that can be allocated a
49 To get around this, isel emits a CopyFromReg from AX and then right shift it
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 176 CopyFromReg, enumerator
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 201 CopyFromReg, enumerator
|