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Searched refs:Cpu (Results 1 – 25 of 50) sorted by relevance

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/external/rust/crates/gdbstub/examples/armv4t_multicore/
Demu.rs14 use armv4t_emu::{reg, Cpu, ExampleMem, Memory, Mode};
23 Cpu, enumerator
37 pub(crate) cpu: Cpu,
38 pub(crate) cop: Cpu,
54 let mut cpu = Cpu::new(); in new()
105 CpuId::Cpu => &mut self.cpu, in step_core()
112 CpuId::Cpu => 0xaa, in step_core()
127 CpuId::Cpu => return Some(Event::Halted), in step_core()
174 for id in [CpuId::Cpu, CpuId::Cop].iter().copied() { in step()
Dgdb.rs34 CpuId::Cpu => Tid::new(1).unwrap(), in cpuid_to_tid()
41 1 => Ok(CpuId::Cpu), in tid_to_cpuid()
111 CpuId::Cpu => &mut self.cpu, in read_registers()
134 CpuId::Cpu => &mut self.cpu, in write_registers()
179 register_thread(cpuid_to_tid(CpuId::Cpu)); in list_active_threads()
/external/google-breakpad/src/tools/mac/upload_system_symbols/
Darch_reader.go47 if header.Cpu == C.kCPU_TYPE_ARM64 && header.SubCpu == C.kCPU_SUBTYPE_ARM64_ALL {
50 if header.Cpu == C.kCPU_TYPE_ARM64 && header.SubCpu == C.kCPU_SUBTYPE_ARM64_E {
53 if header.Cpu == C.kCPU_TYPE_ARM && header.SubCpu == C.kCPU_SUBTYPE_ARM_V7S {
57 cstr := C.GetNXArchInfoName(C.cpu_type_t(header.Cpu), C.cpu_subtype_t(header.SubCpu))
/external/llvm-project/llvm/lib/Target/Lanai/
DLanaiSubtarget.cpp39 LanaiSubtarget::LanaiSubtarget(const Triple &TargetTriple, StringRef Cpu, in LanaiSubtarget() argument
44 : LanaiGenSubtargetInfo(TargetTriple, Cpu, /*TuneCPU*/ Cpu, FeatureString), in LanaiSubtarget()
45 FrameLowering(initializeSubtargetDependencies(Cpu, FeatureString)), in LanaiSubtarget()
DLanaiTargetMachine.cpp57 StringRef Cpu, StringRef FeatureString, in LanaiTargetMachine() argument
62 : LLVMTargetMachine(T, computeDataLayout(), TT, Cpu, FeatureString, Options, in LanaiTargetMachine()
66 Subtarget(TT, Cpu, FeatureString, *this, Options, getCodeModel(), in LanaiTargetMachine()
/external/tensorflow/tensorflow/c/kernels/
Dsummary_op_benchmark_test.cc60 BM_ScalarSummaryDev(Cpu, (5, 10, 100), Base, Tag, 5.2);
62 BM_ScalarSummaryDev(Cpu, (500, 100, 100), LargeShape, Tag, 5.2);
64 BM_ScalarSummaryDev(Cpu, (5, 10, 100), LongTag, longTagParam, 5.2);
66 BM_ScalarSummaryDev(Cpu, (500, 100, 100), LargeValue, Tag, largeValueParam);
/external/autotest/server/cros/res_resource_monitor/
Dtop_test_data.txt3 %Cpu(s): 0.1 us, 0.0 sy, 0.0 ni, 99.9 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
20 %Cpu(s): 0.0 us, 0.0 sy, 0.0 ni,100.0 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
33 %Cpu(s): 0.1 us, 0.0 sy, 0.0 ni, 99.9 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
39 %Cpu(s): 0.0 us, 0.1 sy , 0.0 ni , 99.9 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
45 %Cpu(s): 0.0 us, 0.1 sy, 0.0 ni, 99.9 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
Dtop_field_order_changed.txt3 %Cpu(s): 0.1 us, 0.0 sy, 0.0 ni, 99.9 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
13 %Cpu(s): 90C cputemperature, 0.0 sy, 0.0 hi, -183 secondsTillOverheat, 0.0 id,100.0 ni, 14324 yeta…
21 %Cpu(s): 0.1 us, 0.0 sy, 0.0 ni, 99.9 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st
24 %Cpu(s): 200.12 id, 100.00% sy, 0.94t ni, over9000 us, -204 wa, 0.0 hi, 0.0023 si, 0.0 st
Dtop_whitespace_ridden.txt3 %Cpu(s): 0.1 us, 0.0 sy, 0.0 ni , 99.9 id , 0.0 wa , 0.0 …
20 …%Cpu(s) : 0.0 us , 0.0 sy, 0.0 ni ,…
66 …%Cpu(s) : 0.0 us , 0.0 sy, 0.0 ni ,…
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiSubtarget.cpp39 LanaiSubtarget::LanaiSubtarget(const Triple &TargetTriple, StringRef Cpu, in LanaiSubtarget() argument
44 : LanaiGenSubtargetInfo(TargetTriple, Cpu, FeatureString), in LanaiSubtarget()
45 FrameLowering(initializeSubtargetDependencies(Cpu, FeatureString)), in LanaiSubtarget()
DLanaiTargetMachine.cpp57 StringRef Cpu, StringRef FeatureString, in LanaiTargetMachine() argument
62 : LLVMTargetMachine(T, computeDataLayout(), TT, Cpu, FeatureString, Options, in LanaiTargetMachine()
66 Subtarget(TT, Cpu, FeatureString, *this, Options, getCodeModel(), in LanaiTargetMachine()
/external/llvm/lib/Target/Lanai/
DLanaiSubtarget.cpp40 LanaiSubtarget::LanaiSubtarget(const Triple &TargetTriple, StringRef Cpu, in LanaiSubtarget() argument
45 : LanaiGenSubtargetInfo(TargetTriple, Cpu, FeatureString), in LanaiSubtarget()
46 FrameLowering(initializeSubtargetDependencies(Cpu, FeatureString)), in LanaiSubtarget()
DLanaiTargetMachine.cpp57 StringRef Cpu, StringRef FeatureString, in LanaiTargetMachine() argument
62 : LLVMTargetMachine(T, computeDataLayout(TargetTriple), TT, Cpu, in LanaiTargetMachine()
65 Subtarget(TT, Cpu, FeatureString, *this, Options, CodeModel, OptLevel), in LanaiTargetMachine()
/external/cpuinfo/test/dmesg/
Dalcatel-revvl.log136 [ 18.817566] (6)[102:hps_main]MobiCore mcd: Cpu 7 is going to die
138 [ 18.819717] (6)[102:hps_main]MobiCore mcd: Cpu 7 is dead
152 [ 19.278387] (6)[102:hps_main]MobiCore mcd: Cpu 7 is going to die
154 [ 19.280186] (4)[102:hps_main]MobiCore mcd: Cpu 7 is dead
159 [ 19.477656] (5)[102:hps_main]MobiCore mcd: Cpu 6 is going to die
161 [ 19.479622] (5)[102:hps_main]MobiCore mcd: Cpu 6 is dead
171 [ 19.888368] (6)[102:hps_main]MobiCore mcd: Cpu 7 is going to die
173 [ 19.889983] (6)[102:hps_main]MobiCore mcd: Cpu 7 is dead
209 [ 20.367611] (5)[102:hps_main]MobiCore mcd: Cpu 6 is going to die
211 [ 20.369335] (5)[102:hps_main]MobiCore mcd: Cpu 6 is dead
[all …]
Dmeizu-pro-6s.log1650 [ 1.931788] (8)[1:swapper/0]MobiCore mcd: Cpu 8 is going to die
1657 [ 1.933425] (1)[1:swapper/0]MobiCore mcd: Cpu 8 is dead
2320 [ 2.106913] (0)[213:hps_main]MobiCore mcd: Cpu 3 is going to die
2324 [ 2.108705] (0)[213:hps_main]MobiCore mcd: Cpu 3 is dead
2325 [ 2.108959] (0)[213:hps_main]MobiCore mcd: Cpu 2 is going to die
2328 [ 2.110539] (0)[213:hps_main]MobiCore mcd: Cpu 2 is dead
2329 [ 2.110803] (0)[213:hps_main]MobiCore mcd: Cpu 1 is going to die
2332 [ 2.112331] (0)[213:hps_main]MobiCore mcd: Cpu 1 is dead
2550 [ 2.408583] (4)[213:hps_main]MobiCore mcd: Cpu 1 is going to die
2553 [ 2.409904] (4)[213:hps_main]MobiCore mcd: Cpu 1 is dead
[all …]
/external/llvm-project/clang/lib/Driver/ToolChains/
DHexagon.cpp29 static StringRef getDefaultHvxLength(StringRef Cpu) { in getDefaultHvxLength() argument
30 return llvm::StringSwitch<StringRef>(Cpu) in getDefaultHvxLength()
50 StringRef Cpu, bool &HasHVX) { in handleHVXTargetFeatures() argument
65 HVXFeature = Cpu = A->getValue(); in handleHVXTargetFeatures()
69 HVXFeature = Args.MakeArgString(llvm::Twine("+hvx") + Cpu); in handleHVXTargetFeatures()
84 HVXLength = getDefaultHvxLength(Cpu); in handleHVXTargetFeatures()
109 StringRef Cpu(toolchains::HexagonToolChain::GetTargetCPUVersion(Args)); in getHexagonTargetFeatures() local
112 const bool TinyCore = Cpu.contains('t'); in getHexagonTargetFeatures()
115 Cpu = Cpu.take_front(Cpu.size() - 1); in getHexagonTargetFeatures()
117 handleHVXTargetFeatures(D, Args, Features, Cpu, HasHVX); in getHexagonTargetFeatures()
/external/rust/crates/gdbstub/examples/armv4t/
Demu.rs1 use armv4t_emu::{reg, Cpu, ExampleMem, Memory, Mode};
20 pub(crate) cpu: Cpu,
30 let mut cpu = Cpu::new(); in new()
/external/perfetto/protos/perfetto/trace/system_info/
Dcpu_info.proto23 message Cpu { message
35 repeated Cpu cpus = 1;
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/DebugInfo/CodeView/
DCodeView.h526 CPURegister(CPUType Cpu, codeview::RegisterId Reg) { in CPURegister()
527 this->Cpu = Cpu; in CPURegister()
530 CPUType Cpu; member
/external/llvm-project/llvm/include/llvm/DebugInfo/CodeView/
DCodeView.h526 CPURegister(CPUType Cpu, codeview::RegisterId Reg) { in CPURegister()
527 this->Cpu = Cpu; in CPURegister()
530 CPUType Cpu; member
/external/llvm/include/llvm/LTO/legacy/
DThinLTOCodeGenerator.h160 void setCpu(std::string Cpu) { TMBuilder.MCpu = std::move(Cpu); } in setCpu() argument
/external/llvm-project/llvm/tools/llvm-pdbutil/
DMinimalSymbolDumper.cpp214 static std::string formatMachineType(CPUType Cpu) { in formatMachineType() argument
215 switch (Cpu) { in formatMachineType()
277 return formatUnknownEnum(Cpu); in formatMachineType()
290 static std::string formatRegisterId(RegisterId Id, CPUType Cpu) { in formatRegisterId() argument
291 if (Cpu == CPUType::ARMNT) { in formatRegisterId()
302 } else if (Cpu == CPUType::ARM64) { in formatRegisterId()
328 static std::string formatRegisterId(uint16_t Reg16, CPUType Cpu) { in formatRegisterId() argument
329 return formatRegisterId(RegisterId(Reg16), Cpu); in formatRegisterId()
332 static std::string formatRegisterId(ulittle16_t &Reg16, CPUType Cpu) { in formatRegisterId() argument
333 return formatRegisterId(uint16_t(Reg16), Cpu); in formatRegisterId()
/external/llvm-project/llvm/tools/llvm-exegesis/lib/
DPerfHelper.cpp100 const int Cpu = -1; // measure any processor. in Counter() local
104 FileDescriptor = perf_event_open(&AttrCopy, Pid, Cpu, GroupFd, Flags); in Counter()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/LTO/legacy/
DThinLTOCodeGenerator.h200 void setCpu(std::string Cpu) { TMBuilder.MCpu = std::move(Cpu); } in setCpu() argument
/external/llvm-project/llvm/include/llvm/LTO/legacy/
DThinLTOCodeGenerator.h200 void setCpu(std::string Cpu) { TMBuilder.MCpu = std::move(Cpu); } in setCpu() argument

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