| /external/llvm-project/llvm/unittests/CodeGen/ |
| D | MachineInstrTest.cpp | 62 MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); in TEST()
63 MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false)); in TEST()
66 MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true)); in TEST()
67 MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false)); in TEST()
82 MI3->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); in TEST()
83 MI3->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ true)); in TEST()
86 MI4->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true)); in TEST()
87 MI4->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ false)); in TEST()
138 MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); in TEST()
140 MachineOperand::CreateReg(VirtualReg, /*isDef*/ false)); in TEST()
[all …]
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 65 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, in getFullAddress()
73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, in getFullAddress()
81 MO.push_back(MachineOperand::CreateReg(0, false, false, in getFullAddress()
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 69 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, false, in getFullAddress()
77 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false, in getFullAddress()
85 MO.push_back(MachineOperand::CreateReg(0, false, false, false, false, false, in getFullAddress()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 69 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, false, in getFullAddress()
77 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false, in getFullAddress()
85 MO.push_back(MachineOperand::CreateReg(0, false, false, false, false, false, in getFullAddress()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIFixVGPRCopies.cpp | 60 MachineOperand::CreateReg(AMDGPU::EXEC, false, true)); in runOnMachineFunction()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFixVGPRCopies.cpp | 60 MachineOperand::CreateReg(AMDGPU::EXEC, false, true)); in runOnMachineFunction()
|
| D | SIFixupVectorISel.cpp | 189 NewGlob->addOperand(MF, MachineOperand::CreateReg(IndexReg, false)); in fixupGlobalSaddr()
192 NewGlob->addOperand(MF, MachineOperand::CreateReg(BaseReg, false)); in fixupGlobalSaddr()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCTOCRegDeps.cpp | 121 MI.addOperand(MachineOperand::CreateReg(PPC::X2, in processBlock()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCTOCRegDeps.cpp | 121 MI.addOperand(MachineOperand::CreateReg(TOCReg, in processBlock()
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCTOCRegDeps.cpp | 121 MI.addOperand(MachineOperand::CreateReg(TOCReg, in processBlock()
|
| /external/llvm/lib/CodeGen/ |
| D | LiveVariables.cpp | 247 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
270 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
383 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegKill()
400 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/, in HandlePhysRegKill()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | LiveVariables.cpp | 247 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
270 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
383 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegKill()
400 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/, in HandlePhysRegKill()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | LiveVariables.cpp | 247 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
270 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
383 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegKill()
400 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/, in HandlePhysRegKill()
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonPeephole.cpp | 216 MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); in runOnMachineFunction()
223 MI.addOperand(MachineOperand::CreateReg( in runOnMachineFunction()
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | Thumb2ITBlockPass.cpp | 218 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
247 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonPeephole.cpp | 219 MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); in runOnMachineFunction()
226 MI.addOperand(MachineOperand::CreateReg( in runOnMachineFunction()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | Thumb2ITBlockPass.cpp | 218 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
247 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
|
| D | ARMBaseInstrInfo.h | 468 MachineOperand::CreateReg(PredReg, false)}};
474 return MachineOperand::CreateReg(CCReg, false);
481 return MachineOperand::CreateReg(ARM::CPSR,
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 804 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in addStackMapLiveVars()
852 Ops.push_back(MachineOperand::CreateReg( in selectStackmap()
963 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*isDef=*/true)); in selectPatchpoint()
1012 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in selectPatchpoint()
1018 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in selectPatchpoint()
1031 Ops.push_back(MachineOperand::CreateReg( in selectPatchpoint()
1037 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/true, in selectPatchpoint()
1065 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)), in selectXRayCustomEvent()
1067 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(1)), in selectXRayCustomEvent()
1084 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)), in selectXRayTypedEvent()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 784 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in addStackMapLiveVars()
832 Ops.push_back(MachineOperand::CreateReg( in selectStackmap()
944 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*isDef=*/true)); in selectPatchpoint()
993 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in selectPatchpoint()
999 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in selectPatchpoint()
1012 Ops.push_back(MachineOperand::CreateReg( in selectPatchpoint()
1018 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/true, in selectPatchpoint()
1046 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)), in selectXRayCustomEvent()
1048 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(1)), in selectXRayCustomEvent()
1065 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)), in selectXRayTypedEvent()
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | Thumb2ITBlockPass.cpp | 205 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
234 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonPeephole.cpp | 222 MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); in runOnMachineFunction()
229 MI.addOperand(MachineOperand::CreateReg( in runOnMachineFunction()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 596 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false)); in addStackMapLiveVars()
644 Ops.push_back(MachineOperand::CreateReg( in selectStackmap()
758 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*IsDef=*/true)); in selectPatchpoint()
807 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false)); in selectPatchpoint()
813 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false)); in selectPatchpoint()
826 Ops.push_back(MachineOperand::CreateReg( in selectPatchpoint()
832 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/true, in selectPatchpoint()
1131 Op = MachineOperand::CreateReg(Reg, false); in selectIntrinsicCall()
1147 Op = MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address), in selectIntrinsicCall()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | FunctionLoweringInfo.h | 216 unsigned CreateReg(MVT VT);
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | FunctionLoweringInfo.h | 199 Register CreateReg(MVT VT, bool isDivergent = false);
|