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/external/llvm-project/llvm/test/MC/ARM/
Dd16.s2 …ple thumbv7-unknown-unknown -show-encoding -mattr=+vfp4,-d32 2>&1 | FileCheck %s --check-prefix=D16
6 @ D16: error: invalid instruction, any one of the following would fix this:
7 @ D16-NEXT: vadd.f64 d1, d2, d16
8 @ D16: note: operand must be a register in range [d0, d15]
9 @ D16: note: too many operands for instruction
12 @ D16: error: operand must be a register in range [d0, d15]
13 @ D16-NEXT: vadd.f64 d1, d17, d6
16 @ D16: error: operand must be a register in range [d0, d15]
17 @ D16-NEXT: vadd.f64 d19, d7, d6
20 @ D16: error: operand must be a register in range [d0, d15]
[all …]
/external/llvm/test/MC/ARM/
Dd16.s2 …ple thumbv7-unknown-unknown -show-encoding -mattr=+vfp4,+d16 2>&1 | FileCheck %s --check-prefix=D16
6 @ D16: invalid operand for instruction
7 @ D16-NEXT: vadd.f64 d1, d2, d16
10 @ D16: invalid operand for instruction
11 @ D16-NEXT: vadd.f64 d1, d17, d6
14 @ D16: invalid operand for instruction
15 @ D16-NEXT: vadd.f64 d19, d7, d6
18 @ D16: invalid operand for instruction
19 @ D16-NEXT: vcvt.f64.f32 d22, s4
22 @ D16: invalid operand for instruction
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dstore-hi16.ll2 …einstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,GFX906,GFX9,NO-D16-HI %s
3 …achineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,GFX803,NO-D16-HI %s
11 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
31 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
51 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
70 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
90 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
204 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
205 ; NO-D16-HI-NEXT: flat_store_short v[0:1], v2
222 ; NO-D16-HI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
[all …]
Dload-hi16.ll2 …attr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX906,NO-D16-HI %s
3 …attr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX803,NO-D16-HI %s
80 ; NO-D16-HI: ds_read_u16 v
95 ; NO-D16-HI: ds_read_u16 v
113 ; NO-D16-HI: ds_read_u16 v
131 ; NO-D16-HI: ds_read_u16 v
147 ; NO-D16-HI: ds_read_u16 v
148 ; NO-D16-HI: v_lshlrev_b32_e32 v0, 16, v0
165 ; NO-D16-HI: ds_read_u16 v
183 ; NO-D16-HI: ds_read_u8 v
[all …]
/external/google-breakpad/src/common/linux/
Dsynth_elf.cc53 D16(ET_EXEC); //TODO: allow passing ET_DYN? in ELF()
55 D16(machine); in ELF()
67 D16(addr_size_ == 8 ? sizeof(Elf64_Ehdr) : sizeof(Elf32_Ehdr)); in ELF()
69 D16(addr_size_ == 8 ? sizeof(Elf64_Phdr) : sizeof(Elf32_Phdr)); in ELF()
71 D16(program_count_label_); in ELF()
73 D16(addr_size_ == 8 ? sizeof(Elf64_Shdr) : sizeof(Elf32_Shdr)); in ELF()
75 D16(section_count_label_); in ELF()
77 D16(section_header_string_index_); in ELF()
231 D16(shndx); in AddSymbol()
240 D16(shndx); in AddSymbol()
/external/llvm/test/MC/Disassembler/ARM/
Dd16.txt6 # D16: warning: invalid instruction encoding
10 # D16: warning: invalid instruction encoding
14 # D16: warning: invalid instruction encoding
18 # D16: warning: invalid instruction encoding
22 # D16: warning: invalid instruction encoding
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dd16.txt6 # D16: warning: invalid instruction encoding
10 # D16: warning: invalid instruction encoding
14 # D16: warning: invalid instruction encoding
18 # D16: warning: invalid instruction encoding
22 # D16: warning: invalid instruction encoding
/external/libxaac/decoder/armv7/
Dixheaacd_esbr_qmfsyn64_winadd.s73 VLD1.32 {D16, D17}, [R0], R8
76 VMLAL.S32 Q13, D16, D18
111 VLD1.32 {D16, D17}, [R1], R8
114 VMLAL.S32 Q13, D16, D18
166 VLD1.32 {D16, D17}, [R0], R8
169 VMLAL.S32 Q13, D16, D18
204 VLD1.32 {D16, D17}, [R1], R8
207 VMLAL.S32 Q13, D16, D18
255 VLD1.32 {D16, D17}, [R0], R8
258 VMLAL.S32 Q13, D16, D18
[all …]
Dixheaacd_esbr_cos_sin_mod_loop2.s82 VSHRN.I64 D16, Q8, #32
93 VST1.32 {D16[1]}, [R11], R8
113 VSHRN.I64 D16, Q8, #32
120 VST1.32 {D16[1]}, [R10]!
142 VSHRN.I64 D16, Q8, #32
151 VST1.32 {D16[1]}, [R11], R8
Dixheaacd_sbr_qmfanal32_winadds.s137 VLD2.16 {D15, D16}, [R3]!
144 VLD1.16 D16, [R1], R6
181 VMLAL.S16 Q15, D16, D17
233 VLD2.16 {D15, D16}, [R3]!
237 VLD1.16 D16, [R1], R6
259 VMLAL.S16 Q15, D16, D17
Dixheaacd_overlap_add2.s109 VST1.32 D16[0], [R2], R11
115 VST1.32 D16[1], [R2], R11
138 VST1.32 D16[0], [R2], R11
141 VST1.32 D16[1], [R2], R11
240 VST1.32 D16[0], [R7], R8
242 VST1.32 D16[1], [R7], R8
262 VST1.32 D16[0], [R7], R8
263 VST1.32 D16[1], [R7], R8
Dixheaacd_sbr_qmfsyn64_winadd.s108 VLD1.16 D16, [R1], R8
114 VMLAL.S16 Q13, D17, D16
174 VLD1.16 D16, [R1], R8
215 VMLAL.S16 Q13, D17, D16
263 VLD1.16 D16, [R1], R8
269 VMLAL.S16 Q13, D17, D16
330 VLD1.16 D16, [R1], R8
362 VMLAL.S16 Q13, D17, D16
Dixheaacd_sbr_qmfanal32_winadds_eld.s116 VLD1.16 {D15, D16}, [R3]! @ tmpQmf_c2[2*(n + 128)] load and incremented
125 VLD1.16 D16, [R1], R6
162 VMLAL.S16 Q15, D16, D17
216 VLD1.16 {D15, D16}, [R3]!
220 VLD1.16 D16, [R1], R6
242 VMLAL.S16 Q15, D16, D17
Dixheaacd_dct3_32.s323 VUZP.16 D16, D17
328 VMLAL.U16 Q15, D16, D10
330 VMLSL.U16 Q14, D16, D8
377 VUZP.16 D16, D17
380 VMLAL.U16 Q15, D16, D10
382 VMLSL.U16 Q14, D16, D8
429 VADD.I32 D16, D1, D3
436 VUZP.16 D16, D17
438 VMLAL.U16 Q15, D16, D10
440 VMLSL.U16 Q14, D16, D8
Dixheaacd_post_twiddle.s181 VUZP.16 D16, D17
185 VMULL.U16 Q3, D16, D10
289 VUZP.16 D16, D17
293 VMULL.U16 Q3, D16, D10
389 VUZP.16 D16, D17
393 VMULL.U16 Q3, D16, D10
505 VUZP.16 D16, D17
509 VMULL.U16 Q3, D16, D10
533 VST2.32 {D14, D16}, [R0]!
Dixheaacd_calc_pre_twid.s61 VSHRN.S64 D16, Q8, #32
69 VSUB.I32 D2, D16, D18
/external/libhevc/decoder/arm/
Dihevcd_fmt_conv_420sp_to_rgba8888.s229 VQMOVUN.S16 D16,Q8
233 VZIP.8 D16,D17
253 VST1.32 D16,[R2]!
280 VQMOVUN.S16 D16,Q8
284 VZIP.8 D16,D17
304 VST1.32 D16,[R8]!
360 VQMOVUN.S16 D16,Q8
364 VZIP.8 D16,D17
384 VST1.32 D16,[R2]!
402 VQMOVUN.S16 D16,Q8
[all …]
/external/OpenCSD/decoder/build/win-vs2015/ref_trace_decode_lib/
Dref_trace_decode_lib.sln20 …vs2015\c_api_pkt_print_test\c_api_pkt_print_test.vcxproj", "{3AC169DA-E156-4D16-95DF-73D7302A5606}"
104 {3AC169DA-E156-4D16-95DF-73D7302A5606}.Debug|Win32.ActiveCfg = Debug|Win32
105 {3AC169DA-E156-4D16-95DF-73D7302A5606}.Debug|Win32.Build.0 = Debug|Win32
106 {3AC169DA-E156-4D16-95DF-73D7302A5606}.Debug|x64.ActiveCfg = Debug|x64
107 {3AC169DA-E156-4D16-95DF-73D7302A5606}.Debug|x64.Build.0 = Debug|x64
108 {3AC169DA-E156-4D16-95DF-73D7302A5606}.Debug-dll|Win32.ActiveCfg = Debug-dll|Win32
109 {3AC169DA-E156-4D16-95DF-73D7302A5606}.Debug-dll|Win32.Build.0 = Debug-dll|Win32
110 {3AC169DA-E156-4D16-95DF-73D7302A5606}.Debug-dll|x64.ActiveCfg = Debug-dll|x64
111 {3AC169DA-E156-4D16-95DF-73D7302A5606}.Debug-dll|x64.Build.0 = Debug-dll|x64
112 {3AC169DA-E156-4D16-95DF-73D7302A5606}.Release|Win32.ActiveCfg = Release|Win32
[all …]
/external/google-breakpad/src/common/dwarf/
Dcfi_assembler.h206 CFISection &D16(uint16_t v) { Section::D16(v); return *this; } in D16() function
207 CFISection &D16(Label v) { Section::D16(v); return *this; } in D16() function
/external/libhevc/common/arm/
Dihevc_resi_trans_32x32_a9q.s294 VST1.32 D16,[R2],R10 @ -- dual issued
327 VSWP D16,D9 @R2 transpose2
367 VST1.32 D16,[R2],R10
390 VSWP D16, D11 @ R1
534 VSWP D16, D1 @ R1
570 VST1.32 D16, [R2], R7
615 VSWP D16, D1 @ R1
649 VST1.32 D16, [R2], R7
692 VSWP D16, D1 @ R1
729 VST1.32 D16, [R2], R7
[all …]
Dihevc_sao_band_offset_chroma.s195 VCLE.U8 D16,D1,D30 @vcle_u8(band_table.val[0], vdup_n_u8(16))
196 VORR.U8 D1,D1,D16 @band_table.val[0] = vorr_u8(band_table.val[0], au1_cmp)
205 VCLE.U8 D16,D1,D30 @vcle_u8(band_table.val[0], vdup_n_u8(16))
206 VAND.U8 D1,D1,D16 @band_table.val[0] = vand_u8(band_table.val[0], au1_cmp)
222 …VADD.I8 D16,D12,D30 @band_table_v.val[3] = vadd_u8(band_table_v.val[3], band_p…
234 …VADD.I8 D12,D16,D26 @band_table_v.val[3] = vadd_u8(band_table_v.val[3], vdup_n…
308 VSUB.I8 D16,D14,D30 @vsub_u8(au1_cur_row_deint.val[1], band_pos_v)
316 …VTBX.8 D14,{D9-D12},D16 @vtbx4_u8(au1_cur_row_deint.val[1], band_table_v, vsub_u8(…
362 VSUB.I8 D16,D14,D30 @vsub_u8(au1_cur_row_deint.val[1], band_pos_v)
370 …VTBX.8 D14,{D9-D12},D16 @vtbx4_u8(au1_cur_row_deint.val[1], band_table_v, vsub_u8(…
/external/llvm-project/llvm/test/TableGen/
Dcond-bitlist.td13 def D16 : S<16>;
19 // CHECK: def D16
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIAddIMGInit.cpp81 MachineOperand *D16 = TII->getNamedOperand(MI, AMDGPU::OpName::d16); in runOnMachineFunction() local
88 unsigned D16Val = D16 ? D16->getImm() : 0; in runOnMachineFunction()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIAddIMGInit.cpp81 MachineOperand *D16 = TII->getNamedOperand(MI, AMDGPU::OpName::d16); in runOnMachineFunction() local
89 unsigned D16Val = D16 ? D16->getImm() : 0; in runOnMachineFunction()
/external/google-breakpad/src/processor/
Dsynth_minidump.cc56 D16(system_info.processor_architecture); in SystemInfo()
57 D16(system_info.processor_level); in SystemInfo()
58 D16(system_info.processor_revision); in SystemInfo()
66 D16(system_info.suite_mask); in SystemInfo()
67 D16(system_info.reserved2); // Well, why not? in SystemInfo()
114 D16(*i); in String()

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