| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SchedFalkorDetails.td | 1245 def : InstRW<[FalkorWr_1none_0cyc], (instrs BRK, DCPS1, DCPS2, DCPS3, HINT, HLT, HVC, ISB, SMC, S…
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| D | AArch64SchedKryoDetails.td | 477 (instrs BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, ISB, HINT, SMC, SVC)>;
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| D | AArch64InstrInfo.td | 2152 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
2161 def : InstAlias<"dcps1", (DCPS1 0)>;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedFalkorDetails.td | 1245 def : InstRW<[FalkorWr_1none_0cyc], (instrs BRK, DCPS1, DCPS2, DCPS3, HINT, HLT, HVC, ISB, SMC, S…
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| D | AArch64SchedKryoDetails.td | 477 (instrs BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, ISB, HINT, SMC, SVC)>;
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| D | AArch64InstrInfo.td | 1979 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1988 def : InstAlias<"dcps1", (DCPS1 0)>;
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| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 950 DCPS1 = ExceptionFixed | 0x00A00001, enumerator
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| D | disasm-aarch64.cc | 2311 case DCPS1: in VisitException()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedKryoDetails.td | 478 (instrs BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, ISB, HINT, SMC, SVC)>;
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| D | AArch64InstrInfo.td | 1276 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1285 def : InstAlias<"dcps1", (DCPS1 0)>;
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| /external/capstone/arch/AArch64/ |
| D | AArch64GenAsmWriter.inc | 287 20524U, // DCPS1
2681 0U, // DCPS1
5234 // BRK, DCPS1, DCPS2, DCPS3, HINT, HLT, HVC, SMC, SVC
7776 // (DCPS1 0)
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| D | AArch64GenDisassemblerTables.inc | 7211 /* 30179 */ MCD_OPC_Decode, 142, 2, 213, 1, // Opcode: DCPS1
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmWriter.inc | 1769 73783U, // DCPS1
7159 0U, // DCPS1
11793 // BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, SMC, SVC, TCANCEL
14868 {AArch64::DCPS1, 85, 1 },
15717 // AArch64::DCPS1 - 85
17639 // (DCPS1 0) - 310
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| D | AArch64GenAsmWriter1.inc | 2766 294936U, // DCPS1
8156 0U, // DCPS1
12790 // BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, SMC, SVC, TCANCEL
15589 {AArch64::DCPS1, 85, 1 },
16438 // AArch64::DCPS1 - 85
18360 // (DCPS1 0) - 310
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| D | AArch64GenMCCodeEmitter.inc | 820 UINT64_C(3567255553), // DCPS1
15517 case AArch64::DCPS1:
16749 CEFBS_None, // DCPS1 = 807
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| D | AArch64GenAsmMatcher.inc | 13467 { 906 /* dcps1 */, AArch64::DCPS1, Convert__imm_95_0, AMFBS_None, { }, },
13468 { 906 /* dcps1 */, AArch64::DCPS1, Convert__Imm0_655351_0, AMFBS_None, { MCK_Imm0_65535 }, },
20840 { 906 /* dcps1 */, AArch64::DCPS1, Convert__imm_95_0, AMFBS_None, { }, },
20841 { 906 /* dcps1 */, AArch64::DCPS1, Convert__Imm0_655351_0, AMFBS_None, { MCK_Imm0_65535 }, },
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| D | AArch64GenInstrInfo.inc | 822 DCPS1 = 807,
7706 …UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #807 = DCPS1
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| D | AArch64GenDisassemblerTables.inc | 16864 /* 81969 */ MCD::OPC_Decode, 167, 6, 143, 3, // Opcode: DCPS1
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