1 /*
2 * Copyright (c) 2015 - 2020, Broadcom
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <errno.h>
8
9 #include <common/bl_common.h>
10 #include <common/debug.h>
11 #include <cortex_a72.h>
12 #include <drivers/arm/sp805.h>
13 #include <drivers/console.h>
14 #include <drivers/delay_timer.h>
15 #include <drivers/ti/uart/uart_16550.h>
16 #include <lib/mmio.h>
17 #include <lib/utils_def.h>
18 #include <plat/common/common_def.h>
19 #include <plat/common/platform.h>
20
21 #include <bl33_info.h>
22 #include <chimp.h>
23 #include <cmn_plat_util.h>
24 #include <dmu.h>
25 #include <fsx.h>
26 #include <iommu.h>
27 #include <ncsi.h>
28 #include <paxb.h>
29 #include <paxc.h>
30 #include <platform_def.h>
31 #include <sdio.h>
32 #include <sr_utils.h>
33 #include <timer_sync.h>
34
35 /*******************************************************************************
36 * Perform any BL3-1 platform setup common to ARM standard platforms
37 ******************************************************************************/
38
brcm_stingray_gain_qspi_control(void)39 static void brcm_stingray_gain_qspi_control(void)
40 {
41 if (boot_source_get() != BOOT_SOURCE_QSPI) {
42 if (bcm_chimp_is_nic_mode() &&
43 (!bcm_chimp_handshake_done())) {
44 /*
45 * Last chance to wait for ChiMP firmware to report
46 * "I am done" before grabbing the QSPI
47 */
48 WARN("ChiMP still not booted\n");
49 #ifndef CHIMP_ALWAYS_NEEDS_QSPI
50 WARN("ChiMP is given the last chance to boot (%d s)\n",
51 CHIMP_HANDSHAKE_TIMEOUT_MS / 1000);
52
53 if (!bcm_chimp_wait_handshake()) {
54 ERROR("ChiMP failed to boot\n");
55 } else {
56 INFO("ChiMP booted successfully\n");
57 }
58 #endif
59 }
60
61 #ifndef CHIMP_ALWAYS_NEEDS_QSPI
62 INFO("AP grabs QSPI\n");
63 /*
64 * For QSPI boot sbl/bl1 has already taken care.
65 * For other boot sources QSPI needs to be muxed to
66 * AP for exclusive use
67 */
68 brcm_stingray_set_qspi_mux(1);
69 INFO("AP (bl31) gained control over QSPI\n");
70 #endif
71 }
72 }
73
brcm_stingray_dma_pl330_init(void)74 static void brcm_stingray_dma_pl330_init(void)
75 {
76 unsigned int val;
77
78 VERBOSE("dma pl330 init start\n");
79
80 /* Set DMAC boot_manager_ns = 0x1 */
81 VERBOSE(" - configure boot security state\n");
82 mmio_setbits_32(DMAC_M0_IDM_IO_CONTROL_DIRECT, BOOT_MANAGER_NS);
83 /* Set boot_peripheral_ns[n:0] = 0xffffffff */
84 mmio_write_32(ICFG_DMAC_CONFIG_2, BOOT_PERIPHERAL_NS);
85 /* Set boot_irq_ns[n:0] = 0x0000ffff */
86 mmio_write_32(ICFG_DMAC_CONFIG_3, BOOT_IRQ_NS);
87
88 /* Set DMAC stream_id */
89 VERBOSE(" - configure stream_id = 0x6000\n");
90 val = (DMAC_STREAM_ID << DMAC_SID_SHIFT);
91 mmio_write_32(ICFG_DMAC_SID_ARADDR_CONTROL, val);
92 mmio_write_32(ICFG_DMAC_SID_AWADDR_CONTROL, val);
93
94 /* Reset DMAC */
95 VERBOSE(" - reset dma pl330\n");
96
97 mmio_setbits_32(DMAC_M0_IDM_RESET_CONTROL, 0x1);
98 udelay(500);
99
100 mmio_clrbits_32(DMAC_M0_IDM_RESET_CONTROL, 0x1);
101 udelay(500);
102
103 INFO("dma pl330 init done\n");
104 }
105
brcm_stingray_spi_pl022_init(uintptr_t idm_reset_control)106 static void brcm_stingray_spi_pl022_init(uintptr_t idm_reset_control)
107 {
108 VERBOSE("spi pl022 init start\n");
109
110 /* Reset APB SPI bridge */
111 VERBOSE(" - reset apb spi bridge\n");
112 mmio_setbits_32(idm_reset_control, 0x1);
113 udelay(500);
114
115 mmio_clrbits_32(idm_reset_control, 0x1);
116 udelay(500);
117
118 INFO("spi pl022 init done\n");
119 }
120
121 #define CDRU_SATA_RESET_N \
122 BIT(CDRU_MISC_RESET_CONTROL__CDRU_SATA_RESET_N_R)
123 #define CDRU_MISC_CLK_SATA \
124 BIT(CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_SATA_CLK_EN_R)
125 #define CCN_CONFIG_CLK_ENABLE (1 << 2)
126 #define MMU_CONFIG_CLK_ENABLE (0x3F << 16)
127
128 #define SATA_SATA_TOP_CTRL_BUS_CTRL (SATA_BASE + 0x2044)
129 #define DMA_BIT_CTRL_MASK 0x003
130 #define DMA_DESCR_ENDIAN_CTRL (DMA_BIT_CTRL_MASK << 0x002)
131 #define DMA_DATA_ENDIAN_CTRL (DMA_BIT_CTRL_MASK << 0x004)
132
133 #define SATA_PORT_SATA3_PCB_REG8 (SATA_BASE + 0x2320)
134 #define SATA_PORT_SATA3_PCB_REG11 (SATA_BASE + 0x232c)
135 #define SATA_PORT_SATA3_PCB_BLOCK_ADDR (SATA_BASE + 0x233c)
136
137 #define SATA3_AFE_TXRX_ACTRL 0x1d0
138 /* TXDriver swing setting is 800mV */
139 #define DFS_SWINGNOPE_VALUE (0x0 << 6)
140 #define DFS_SWINGNOPE_MASK (0x3 << 6)
141
142 #define DFS_SWINGPE_VALUE (0x1 << 4)
143 #define DFS_SWINGPE_MASK (0x3 << 4)
144
145 #define DFS_INJSTRENGTH_VALUE (0x0 << 4)
146 #define DFS_INJSTRENGTH_MASK (0x3 << 4)
147
148 #define DFS_INJEN (0x1 << 3)
149
150 #define SATA_CORE_MEM_CTRL (SATA_BASE + 0x3a08)
151 #define SATA_CORE_MEM_CTRL_ISO BIT(0)
152 #define SATA_CORE_MEM_CTRL_ARRPOWEROKIN BIT(1)
153 #define SATA_CORE_MEM_CTRL_ARRPOWERONIN BIT(2)
154 #define SATA_CORE_MEM_CTRL_POWEROKIN BIT(3)
155 #define SATA_CORE_MEM_CTRL_POWERONIN BIT(4)
156
157 #define SATA0_IDM_RESET_CONTROL (SATA_BASE + 0x500800)
158 #define SATA_APBT0_IDM_IO_CONTROL_DIRECT (SATA_BASE + 0x51a408)
159 #define IO_CONTROL_DIRECT_CLK_ENABLE BIT(0)
160 #define SATA_APBT0_IDM_RESET_CONTROL (SATA_BASE + 0x51a800)
161 #define IDM_RESET_CONTROL_RESET BIT(0)
162
163 #define NIC400_SATA_NOC_SECURITY1 0x6830000c
164 #define SATA_NOC_SECURITY1_FIELD 0xf
165 #define NIC400_SATA_NOC_SECURITY2 0x68300010
166 #define SATA_NOC_SECURITY2_FIELD 0xf
167 #define NIC400_SATA_NOC_SECURITY3 0x68300014
168 #define SATA_NOC_SECURITY3_FIELD 0x1
169 #define NIC400_SATA_NOC_SECURITY4 0x68300018
170 #define SATA_NOC_SECURITY4_FIELD 0x1
171 #define NIC400_SATA_NOC_SECURITY5 0x6830001c
172 #define SATA_NOC_SECURITY5_FIELD 0xf
173 #define NIC400_SATA_NOC_SECURITY6 0x68300020
174 #define SATA_NOC_SECURITY6_FIELD 0x1
175 #define NIC400_SATA_NOC_SECURITY7 0x68300024
176 #define SATA_NOC_SECURITY7_FIELD 0xf
177 #define NIC400_SATA_NOC_SECURITY8 0x68300028
178 #define SATA_NOC_SECURITY8_FIELD 0xf
179 #define NIC400_SATA_NOC_SECURITY9 0x6830002c
180 #define SATA_NOC_SECURITY9_FIELD 0x1
181
182 #define SATA_APBT_IDM_PORT_REG(port, reg) \
183 (((port/4) << 12) + reg)
184
185 #define SATA_IDM_PORT_REG(port, reg) ((port << 12) + reg)
186
187 #define SATA_PORT_REG(port, reg) \
188 (((port%4) << 16) + ((port/4) << 20) + reg)
189
190 #define MAX_SATA_PORTS 8
191 #define USE_SATA_PORTS 8
192
193 #ifdef USE_SATA
194 static const uint8_t sr_b0_sata_port[MAX_SATA_PORTS] = {
195 0, 1, 2, 3, 4, 5, 6, 7
196 };
197
brcm_stingray_get_sata_port(unsigned int port)198 static uint32_t brcm_stingray_get_sata_port(unsigned int port)
199 {
200 return sr_b0_sata_port[port];
201 }
202
brcm_stingray_sata_init(void)203 static void brcm_stingray_sata_init(void)
204 {
205 unsigned int port = 0;
206 uint32_t sata_port;
207
208 mmio_setbits_32(CDRU_MISC_CLK_ENABLE_CONTROL,
209 CDRU_MISC_CLK_SATA);
210
211 mmio_clrbits_32(CDRU_MISC_RESET_CONTROL, CDRU_SATA_RESET_N);
212 mmio_setbits_32(CDRU_MISC_RESET_CONTROL, CDRU_SATA_RESET_N);
213
214 for (port = 0; port < USE_SATA_PORTS; port++) {
215
216 sata_port = brcm_stingray_get_sata_port(port);
217 mmio_write_32(SATA_APBT_IDM_PORT_REG(sata_port,
218 SATA_APBT0_IDM_RESET_CONTROL),
219 0x0);
220 mmio_setbits_32(SATA_APBT_IDM_PORT_REG(sata_port,
221 SATA_APBT0_IDM_IO_CONTROL_DIRECT),
222 IO_CONTROL_DIRECT_CLK_ENABLE);
223 mmio_write_32(SATA_IDM_PORT_REG(sata_port,
224 SATA0_IDM_RESET_CONTROL),
225 0x0);
226
227 mmio_setbits_32(SATA_PORT_REG(sata_port, SATA_CORE_MEM_CTRL),
228 SATA_CORE_MEM_CTRL_ARRPOWERONIN);
229 mmio_setbits_32(SATA_PORT_REG(sata_port, SATA_CORE_MEM_CTRL),
230 SATA_CORE_MEM_CTRL_ARRPOWEROKIN);
231 mmio_setbits_32(SATA_PORT_REG(sata_port, SATA_CORE_MEM_CTRL),
232 SATA_CORE_MEM_CTRL_POWERONIN);
233 mmio_setbits_32(SATA_PORT_REG(sata_port, SATA_CORE_MEM_CTRL),
234 SATA_CORE_MEM_CTRL_POWEROKIN);
235 mmio_clrbits_32(SATA_PORT_REG(sata_port, SATA_CORE_MEM_CTRL),
236 SATA_CORE_MEM_CTRL_ISO);
237
238 mmio_clrbits_32(SATA_PORT_REG(sata_port,
239 SATA_SATA_TOP_CTRL_BUS_CTRL),
240 (DMA_DESCR_ENDIAN_CTRL | DMA_DATA_ENDIAN_CTRL));
241 }
242
243 mmio_setbits_32(NIC400_SATA_NOC_SECURITY1, SATA_NOC_SECURITY1_FIELD);
244 mmio_setbits_32(NIC400_SATA_NOC_SECURITY2, SATA_NOC_SECURITY2_FIELD);
245 mmio_setbits_32(NIC400_SATA_NOC_SECURITY3, SATA_NOC_SECURITY3_FIELD);
246 mmio_setbits_32(NIC400_SATA_NOC_SECURITY4, SATA_NOC_SECURITY4_FIELD);
247 mmio_setbits_32(NIC400_SATA_NOC_SECURITY5, SATA_NOC_SECURITY5_FIELD);
248 mmio_setbits_32(NIC400_SATA_NOC_SECURITY6, SATA_NOC_SECURITY6_FIELD);
249 mmio_setbits_32(NIC400_SATA_NOC_SECURITY7, SATA_NOC_SECURITY7_FIELD);
250 mmio_setbits_32(NIC400_SATA_NOC_SECURITY8, SATA_NOC_SECURITY8_FIELD);
251 mmio_setbits_32(NIC400_SATA_NOC_SECURITY9, SATA_NOC_SECURITY9_FIELD);
252
253 INFO("sata init done\n");
254 }
255 #else
poweroff_sata_pll(void)256 static void poweroff_sata_pll(void)
257 {
258 /*
259 * SATA subsystem is clocked by LCPLL0 which is enabled by
260 * default by bootrom. Poweroff the PLL if SATA is not used
261 */
262
263 /* enable isolation */
264 mmio_setbits_32(CRMU_AON_CTRL1,
265 BIT(CRMU_AON_CTRL1__LCPLL0_ISO_IN));
266
267 /* Power off the SATA PLL/LDO */
268 mmio_clrbits_32(CRMU_AON_CTRL1,
269 (BIT(CRMU_AON_CTRL1__LCPLL0_PWRON_LDO) |
270 BIT(CRMU_AON_CTRL1__LCPLL0_PWR_ON)));
271 }
272 #endif
273
274 #ifdef USE_AMAC
275 #ifdef EMULATION_SETUP
276 #define ICFG_AMAC_STRAP_CONFIG (HSLS_ICFG_REGS_BASE + 0xa5c)
277 #define ICFG_AMAC_STRAP_DLL_BYPASS (1 << 2)
278 #endif
279 #define ICFG_AMAC_MAC_CTRL_REG (HSLS_ICFG_REGS_BASE + 0xa6c)
280 #define ICFG_AMAC_MAC_FULL_DUPLEX (1 << 1)
281 #define ICFG_AMAC_RGMII_PHY_CONFIG (HSLS_ICFG_REGS_BASE + 0xa60)
282 #define ICFG_AMAC_SID_CONTROL (HSLS_ICFG_REGS_BASE + 0xb10)
283 #define ICFG_AMAC_SID_SHIFT 5
284 #define ICFG_AMAC_SID_AWADDR_OFFSET 0x0
285 #define ICFG_AMAC_SID_ARADDR_OFFSET 0x4
286 #define AMAC_RPHY_1000_DATARATE (1 << 20)
287 #define AMAC_RPHY_FULL_DUPLEX (1 << 5)
288 #define AMAC_RPHY_SPEED_OFFSET 2
289 #define AMAC_RPHY_SPEED_MASK (7 << AMAC_RPHY_SPEED_OFFSET)
290 #define AMAC_RPHY_1G_SPEED (2 << AMAC_RPHY_SPEED_OFFSET)
291 #define ICFG_AMAC_MEM_PWR_CTRL (HSLS_ICFG_REGS_BASE + 0xa68)
292 #define AMAC_ISO BIT(9)
293 #define AMAC_STDBY BIT(8)
294 #define AMAC_ARRPOWEROKIN BIT(7)
295 #define AMAC_ARRPOWERONIN BIT(6)
296 #define AMAC_POWEROKIN BIT(5)
297 #define AMAC_POWERONIN BIT(4)
298
299 #define AMAC_IDM0_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x4408)
300 #define AMAC_IDM0_ARCACHE_OFFSET 16
301 #define AMAC_IDM0_AWCACHE_OFFSET 7
302 #define AMAC_IDM0_ARCACHE_MASK (0xF << AMAC_IDM0_ARCACHE_OFFSET)
303 #define AMAC_IDM0_AWCACHE_MASK (0xF << AMAC_IDM0_AWCACHE_OFFSET)
304 /* ARCACHE - AWCACHE is 0xB7 for write-back no allocate */
305 #define AMAC_IDM0_ARCACHE_VAL (0xb << AMAC_IDM0_ARCACHE_OFFSET)
306 #define AMAC_IDM0_AWCACHE_VAL (0x7 << AMAC_IDM0_AWCACHE_OFFSET)
307
brcm_stingray_amac_init(void)308 static void brcm_stingray_amac_init(void)
309 {
310 unsigned int val;
311 uintptr_t icfg_amac_sid = ICFG_AMAC_SID_CONTROL;
312
313 VERBOSE("amac init start\n");
314
315 val = SR_SID_VAL(0x3, 0x0, 0x4) << ICFG_AMAC_SID_SHIFT;
316 mmio_write_32(icfg_amac_sid + ICFG_AMAC_SID_AWADDR_OFFSET, val);
317 mmio_write_32(icfg_amac_sid + ICFG_AMAC_SID_ARADDR_OFFSET, val);
318
319 mmio_setbits_32(ICFG_AMAC_MEM_PWR_CTRL, AMAC_ARRPOWEROKIN);
320 mmio_setbits_32(ICFG_AMAC_MEM_PWR_CTRL, AMAC_ARRPOWERONIN);
321 mmio_setbits_32(ICFG_AMAC_MEM_PWR_CTRL, AMAC_POWEROKIN);
322 mmio_setbits_32(ICFG_AMAC_MEM_PWR_CTRL, AMAC_POWERONIN);
323 mmio_clrbits_32(ICFG_AMAC_MEM_PWR_CTRL, AMAC_ISO);
324 mmio_write_32(APBR_IDM_RESET_CONTROL, 0x0);
325 mmio_clrsetbits_32(ICFG_AMAC_RGMII_PHY_CONFIG, AMAC_RPHY_SPEED_MASK,
326 AMAC_RPHY_1G_SPEED); /*1 Gbps line rate*/
327 /* 1000 datarate set */
328 mmio_setbits_32(ICFG_AMAC_RGMII_PHY_CONFIG, AMAC_RPHY_1000_DATARATE);
329 /* full duplex */
330 mmio_setbits_32(ICFG_AMAC_RGMII_PHY_CONFIG, AMAC_RPHY_FULL_DUPLEX);
331 #ifdef EMULATION_SETUP
332 /* DLL bypass */
333 mmio_setbits_32(ICFG_AMAC_STRAP_CONFIG, ICFG_AMAC_STRAP_DLL_BYPASS);
334 #endif
335 /* serdes full duplex */
336 mmio_setbits_32(ICFG_AMAC_MAC_CTRL_REG, ICFG_AMAC_MAC_FULL_DUPLEX);
337 mmio_clrsetbits_32(AMAC_IDM0_IO_CONTROL_DIRECT, AMAC_IDM0_ARCACHE_MASK,
338 AMAC_IDM0_ARCACHE_VAL);
339 mmio_clrsetbits_32(AMAC_IDM0_IO_CONTROL_DIRECT, AMAC_IDM0_AWCACHE_MASK,
340 AMAC_IDM0_AWCACHE_VAL);
341 INFO("amac init done\n");
342 }
343 #endif /* USE_AMAC */
344
brcm_stingray_pka_meminit(void)345 static void brcm_stingray_pka_meminit(void)
346 {
347 uintptr_t icfg_mem_ctrl = ICFG_PKA_MEM_PWR_CTRL;
348
349 VERBOSE("pka meminit start\n");
350
351 VERBOSE(" - arrpoweron\n");
352 mmio_setbits_32(icfg_mem_ctrl,
353 ICFG_PKA_MEM_PWR_CTRL__ARRPOWERONIN);
354 while (!(mmio_read_32(icfg_mem_ctrl) &
355 ICFG_PKA_MEM_PWR_CTRL__ARRPOWERONOUT))
356 ;
357
358 VERBOSE(" - arrpowerok\n");
359 mmio_setbits_32(icfg_mem_ctrl,
360 ICFG_PKA_MEM_PWR_CTRL__ARRPOWEROKIN);
361 while (!(mmio_read_32(icfg_mem_ctrl) &
362 ICFG_PKA_MEM_PWR_CTRL__ARRPOWEROKOUT))
363 ;
364
365 VERBOSE(" - poweron\n");
366 mmio_setbits_32(icfg_mem_ctrl,
367 ICFG_PKA_MEM_PWR_CTRL__POWERONIN);
368 while (!(mmio_read_32(icfg_mem_ctrl) &
369 ICFG_PKA_MEM_PWR_CTRL__POWERONOUT))
370 ;
371
372 VERBOSE(" - powerok\n");
373 mmio_setbits_32(icfg_mem_ctrl,
374 ICFG_PKA_MEM_PWR_CTRL__POWEROKIN);
375 while (!(mmio_read_32(icfg_mem_ctrl) &
376 ICFG_PKA_MEM_PWR_CTRL__POWEROKOUT))
377 ;
378
379 /* Wait sometime */
380 mdelay(1);
381
382 VERBOSE(" - remove isolation\n");
383 mmio_clrbits_32(icfg_mem_ctrl, ICFG_PKA_MEM_PWR_CTRL__ISO);
384
385 INFO("pka meminit done\n");
386 }
387
brcm_stingray_smmu_init(void)388 static void brcm_stingray_smmu_init(void)
389 {
390 unsigned int val;
391 uintptr_t smmu_base = SMMU_BASE;
392
393 VERBOSE("smmu init start\n");
394
395 /* Configure SCR0 */
396 VERBOSE(" - configure scr0\n");
397 val = mmio_read_32(smmu_base + 0x0);
398 val |= (0x1 << 12);
399 mmio_write_32(smmu_base + 0x0, val);
400
401 /* Reserve context banks for secure masters */
402 arm_smmu_reserve_secure_cntxt();
403
404 /* Print configuration */
405 VERBOSE(" - scr0=0x%x scr1=0x%x scr2=0x%x\n",
406 mmio_read_32(smmu_base + 0x0),
407 mmio_read_32(smmu_base + 0x4),
408 mmio_read_32(smmu_base + 0x8));
409
410 VERBOSE(" - idr0=0x%x idr1=0x%x idr2=0x%x\n",
411 mmio_read_32(smmu_base + 0x20),
412 mmio_read_32(smmu_base + 0x24),
413 mmio_read_32(smmu_base + 0x28));
414
415 VERBOSE(" - idr3=0x%x idr4=0x%x idr5=0x%x\n",
416 mmio_read_32(smmu_base + 0x2c),
417 mmio_read_32(smmu_base + 0x30),
418 mmio_read_32(smmu_base + 0x34));
419
420 VERBOSE(" - idr6=0x%x idr7=0x%x\n",
421 mmio_read_32(smmu_base + 0x38),
422 mmio_read_32(smmu_base + 0x3c));
423
424 INFO("smmu init done\n");
425 }
426
brcm_stingray_dma_pl330_meminit(void)427 static void brcm_stingray_dma_pl330_meminit(void)
428 {
429 uintptr_t icfg_mem_ctrl = ICFG_DMAC_MEM_PWR_CTRL;
430
431 VERBOSE("dmac meminit start\n");
432
433 VERBOSE(" - arrpoweron\n");
434 mmio_setbits_32(icfg_mem_ctrl,
435 ICFG_DMAC_MEM_PWR_CTRL__ARRPOWERONIN);
436 while (!(mmio_read_32(icfg_mem_ctrl) &
437 ICFG_DMAC_MEM_PWR_CTRL__ARRPOWERONOUT))
438 ;
439
440 VERBOSE(" - arrpowerok\n");
441 mmio_setbits_32(icfg_mem_ctrl,
442 ICFG_DMAC_MEM_PWR_CTRL__ARRPOWEROKIN);
443 while (!(mmio_read_32(icfg_mem_ctrl) &
444 ICFG_DMAC_MEM_PWR_CTRL__ARRPOWEROKOUT))
445 ;
446
447 VERBOSE(" - poweron\n");
448 mmio_setbits_32(icfg_mem_ctrl,
449 ICFG_DMAC_MEM_PWR_CTRL__POWERONIN);
450 while (!(mmio_read_32(icfg_mem_ctrl) &
451 ICFG_DMAC_MEM_PWR_CTRL__POWERONOUT))
452 ;
453
454 VERBOSE(" - powerok\n");
455 mmio_setbits_32(icfg_mem_ctrl,
456 ICFG_DMAC_MEM_PWR_CTRL__POWEROKIN);
457 while (!(mmio_read_32(icfg_mem_ctrl) &
458 ICFG_DMAC_MEM_PWR_CTRL__POWEROKOUT))
459 ;
460
461 /* Wait sometime */
462 mdelay(1);
463
464 VERBOSE(" - remove isolation\n");
465 mmio_clrbits_32(icfg_mem_ctrl, ICFG_DMAC_MEM_PWR_CTRL__ISO);
466
467 INFO("dmac meminit done\n");
468 }
469
470 /* program the crmu access ranges for allowing non sec access*/
brcm_stingray_crmu_access_init(void)471 static void brcm_stingray_crmu_access_init(void)
472 {
473 /* Enable 0x6641c001 - 0x6641c701 for non secure access */
474 mmio_write_32(CRMU_CORE_ADDR_RANGE0_LOW, 0x6641c001);
475 mmio_write_32(CRMU_CORE_ADDR_RANGE0_LOW + 0x4, 0x6641c701);
476
477 /* Enable 0x6641d001 - 0x66424b01 for non secure access */
478 mmio_write_32(CRMU_CORE_ADDR_RANGE1_LOW, 0x6641d001);
479 mmio_write_32(CRMU_CORE_ADDR_RANGE1_LOW + 0x4, 0x66424b01);
480
481 /* Enable 0x66425001 - 0x66425f01 for non secure access */
482 mmio_write_32(CRMU_CORE_ADDR_RANGE2_LOW, 0x66425001);
483 mmio_write_32(CRMU_CORE_ADDR_RANGE2_LOW + 0x4, 0x66425f01);
484
485 INFO("crmu access init done\n");
486 }
487
brcm_stingray_scr_init(void)488 static void brcm_stingray_scr_init(void)
489 {
490 unsigned int val;
491 uintptr_t scr_base = SCR_BASE;
492 unsigned int clr_mask = SCR_AXCACHE_CONFIG_MASK;
493 unsigned int set_mask = SCR_TBUX_AXCACHE_CONFIG;
494
495 VERBOSE("scr init start\n");
496
497 /* awdomain=0x1 and ardomain=0x1 */
498 mmio_clrsetbits_32(scr_base + 0x0, clr_mask, set_mask);
499 val = mmio_read_32(scr_base + 0x0);
500 VERBOSE(" - set tbu0_config=0x%x\n", val);
501
502 /* awdomain=0x1 and ardomain=0x1 */
503 mmio_clrsetbits_32(scr_base + 0x4, clr_mask, set_mask);
504 val = mmio_read_32(scr_base + 0x4);
505 VERBOSE(" - set tbu1_config=0x%x\n", val);
506
507 /* awdomain=0x1 and ardomain=0x1 */
508 mmio_clrsetbits_32(scr_base + 0x8, clr_mask, set_mask);
509 val = mmio_read_32(scr_base + 0x8);
510 VERBOSE(" - set tbu2_config=0x%x\n", val);
511
512 /* awdomain=0x1 and ardomain=0x1 */
513 mmio_clrsetbits_32(scr_base + 0xc, clr_mask, set_mask);
514 val = mmio_read_32(scr_base + 0xc);
515 VERBOSE(" - set tbu3_config=0x%x\n", val);
516
517 /* awdomain=0x1 and ardomain=0x1 */
518 mmio_clrsetbits_32(scr_base + 0x10, clr_mask, set_mask);
519 val = mmio_read_32(scr_base + 0x10);
520 VERBOSE(" - set tbu4_config=0x%x\n", val);
521
522 /* awdomain=0x0 and ardomain=0x0 */
523 mmio_clrbits_32(scr_base + 0x14, clr_mask);
524 val = mmio_read_32(scr_base + 0x14);
525 VERBOSE(" - set gic_config=0x%x\n", val);
526
527 INFO("scr init done\n");
528 }
529
brcm_stingray_hsls_tzpcprot_init(void)530 static void brcm_stingray_hsls_tzpcprot_init(void)
531 {
532 unsigned int val;
533 uintptr_t tzpcdecprot_base = HSLS_TZPC_BASE;
534
535 VERBOSE("hsls tzpcprot init start\n");
536
537 /* Treat third-party masters as non-secured */
538 val = 0;
539 val |= BIT(6); /* SDIO1 */
540 val |= BIT(5); /* SDIO0 */
541 val |= BIT(0); /* AMAC */
542 mmio_write_32(tzpcdecprot_base + 0x810, val);
543
544 /* Print TZPC decode status registers */
545 VERBOSE(" - tzpcdecprot0=0x%x\n",
546 mmio_read_32(tzpcdecprot_base + 0x800));
547
548 VERBOSE(" - tzpcdecprot1=0x%x\n",
549 mmio_read_32(tzpcdecprot_base + 0x80c));
550
551 INFO("hsls tzpcprot init done\n");
552 }
553
554 #ifdef USE_I2S
555 #define ICFG_AUDIO_POWER_CTRL (HSLS_ICFG_REGS_BASE + 0xaa8)
556 #define ICFG_AUDIO_POWER_CTRL__POWERONIN BIT(0)
557 #define ICFG_AUDIO_POWER_CTRL__POWEROKIN BIT(1)
558 #define ICFG_AUDIO_POWER_CTRL__ARRPOWERONIN BIT(2)
559 #define ICFG_AUDIO_POWER_CTRL__ARRPOWEROKIN BIT(3)
560 #define ICFG_AUDIO_POWER_CTRL__POWERONOUT BIT(4)
561 #define ICFG_AUDIO_POWER_CTRL__POWEROKOUT BIT(5)
562 #define ICFG_AUDIO_POWER_CTRL__ARRPOWERONOUT BIT(6)
563 #define ICFG_AUDIO_POWER_CTRL__ARRPOWEROKOUT BIT(7)
564 #define ICFG_AUDIO_POWER_CTRL__ISO BIT(8)
565 #define ICFG_AUDIO_SID_CONTROL (HSLS_ICFG_REGS_BASE + 0xaf8)
566 #define ICFG_AUDIO_SID_SHIFT 5
567 #define ICFG_AUDIO_SID_AWADDR_OFFSET 0x0
568 #define ICFG_AUDIO_SID_ARADDR_OFFSET 0x4
569
570 #define I2S_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0x1800)
571 #define I2S_IDM_IO_CONTROL (HSLS_IDM_REGS_BASE + 0x1408)
572 #define IO_CONTROL_CLK_ENABLE BIT(0)
573 #define I2S_IDM0_ARCACHE_OFFSET 16
574 #define I2S_IDM0_AWCACHE_OFFSET 20
575 #define I2S_IDM0_ARCACHE_MASK (0xF << I2S_IDM0_ARCACHE_OFFSET)
576 #define I2S_IDM0_AWCACHE_MASK (0xF << I2S_IDM0_AWCACHE_OFFSET)
577 /* ARCACHE - AWCACHE is 0x22 Normal Non-cacheable Non-bufferable. */
578 #define I2S_IDM0_ARCACHE_VAL (0x2 << I2S_IDM0_ARCACHE_OFFSET)
579 #define I2S_IDM0_AWCACHE_VAL (0x2 << I2S_IDM0_AWCACHE_OFFSET)
580
brcm_stingray_audio_init(void)581 static void brcm_stingray_audio_init(void)
582 {
583 unsigned int val;
584 uintptr_t icfg_mem_ctrl = ICFG_AUDIO_POWER_CTRL;
585 uintptr_t icfg_audio_sid = ICFG_AUDIO_SID_CONTROL;
586
587 mmio_write_32(I2S_RESET_CONTROL, 0x0);
588
589 mmio_clrsetbits_32(I2S_IDM_IO_CONTROL, I2S_IDM0_ARCACHE_MASK,
590 I2S_IDM0_ARCACHE_VAL);
591
592 mmio_clrsetbits_32(I2S_IDM_IO_CONTROL, I2S_IDM0_AWCACHE_MASK,
593 I2S_IDM0_AWCACHE_VAL);
594
595 mmio_setbits_32(I2S_IDM_IO_CONTROL, IO_CONTROL_CLK_ENABLE);
596
597 VERBOSE("audio meminit start\n");
598
599 VERBOSE(" - configure stream_id = 0x6001\n");
600 val = SR_SID_VAL(0x3, 0x0, 0x1) << ICFG_AUDIO_SID_SHIFT;
601 mmio_write_32(icfg_audio_sid + ICFG_AUDIO_SID_AWADDR_OFFSET, val);
602 mmio_write_32(icfg_audio_sid + ICFG_AUDIO_SID_ARADDR_OFFSET, val);
603
604 VERBOSE(" - arrpoweron\n");
605 mmio_setbits_32(icfg_mem_ctrl,
606 ICFG_AUDIO_POWER_CTRL__ARRPOWERONIN);
607 while (!(mmio_read_32(icfg_mem_ctrl) &
608 ICFG_AUDIO_POWER_CTRL__ARRPOWERONOUT))
609 ;
610
611 VERBOSE(" - arrpowerok\n");
612 mmio_setbits_32(icfg_mem_ctrl,
613 ICFG_AUDIO_POWER_CTRL__ARRPOWEROKIN);
614 while (!(mmio_read_32(icfg_mem_ctrl) &
615 ICFG_AUDIO_POWER_CTRL__ARRPOWEROKOUT))
616 ;
617
618 VERBOSE(" - poweron\n");
619 mmio_setbits_32(icfg_mem_ctrl,
620 ICFG_AUDIO_POWER_CTRL__POWERONIN);
621 while (!(mmio_read_32(icfg_mem_ctrl) &
622 ICFG_AUDIO_POWER_CTRL__POWERONOUT))
623 ;
624
625 VERBOSE(" - powerok\n");
626 mmio_setbits_32(icfg_mem_ctrl,
627 ICFG_AUDIO_POWER_CTRL__POWEROKIN);
628 while (!(mmio_read_32(icfg_mem_ctrl) &
629 ICFG_AUDIO_POWER_CTRL__POWEROKOUT))
630 ;
631
632 /* Wait sometime */
633 mdelay(1);
634
635 VERBOSE(" - remove isolation\n");
636 mmio_clrbits_32(icfg_mem_ctrl, ICFG_AUDIO_POWER_CTRL__ISO);
637
638 INFO("audio meminit done\n");
639 }
640 #endif /* USE_I2S */
641
642 /*
643 * These defines do not match the regfile but they are renamed in a way such
644 * that they are much more readible
645 */
646
647 #define SCR_GPV_SMMU_NS (SCR_GPV_BASE + 0x28)
648 #define SCR_GPV_GIC500_NS (SCR_GPV_BASE + 0x34)
649 #define HSLS_GPV_NOR_S0_NS (HSLS_GPV_BASE + 0x14)
650 #define HSLS_GPV_IDM1_NS (HSLS_GPV_BASE + 0x18)
651 #define HSLS_GPV_IDM2_NS (HSLS_GPV_BASE + 0x1c)
652 #define HSLS_SDIO0_SLAVE_NS (HSLS_GPV_BASE + 0x20)
653 #define HSLS_SDIO1_SLAVE_NS (HSLS_GPV_BASE + 0x24)
654 #define HSLS_GPV_APBY_NS (HSLS_GPV_BASE + 0x2c)
655 #define HSLS_GPV_APBZ_NS (HSLS_GPV_BASE + 0x30)
656 #define HSLS_GPV_APBX_NS (HSLS_GPV_BASE + 0x34)
657 #define HSLS_GPV_APBS_NS (HSLS_GPV_BASE + 0x38)
658 #define HSLS_GPV_QSPI_S0_NS (HSLS_GPV_BASE + 0x68)
659 #define HSLS_GPV_APBR_NS (HSLS_GPV_BASE + 0x6c)
660 #define FS4_CRYPTO_GPV_RM_SLAVE_NS (FS4_CRYPTO_GPV_BASE + 0x8)
661 #define FS4_CRYPTO_GPV_APB_SWITCH_NS (FS4_CRYPTO_GPV_BASE + 0xc)
662 #define FS4_RAID_GPV_RM_SLAVE_NS (FS4_RAID_GPV_BASE + 0x8)
663 #define FS4_RAID_GPV_APB_SWITCH_NS (FS4_RAID_GPV_BASE + 0xc)
664 #define FS4_CRYPTO_IDM_NS (NIC400_FS_NOC_ROOT + 0x1c)
665 #define FS4_RAID_IDM_NS (NIC400_FS_NOC_ROOT + 0x28)
666
667 #define FS4_CRYPTO_RING_COUNT 32
668 #define FS4_CRYPTO_DME_COUNT 10
669 #define FS4_CRYPTO_AE_COUNT 10
670 #define FS4_CRYPTO_START_STREAM_ID 0x4000
671 #define FS4_CRYPTO_MSI_DEVICE_ID 0x4100
672
673 #define FS4_RAID_RING_COUNT 32
674 #define FS4_RAID_DME_COUNT 8
675 #define FS4_RAID_AE_COUNT 8
676 #define FS4_RAID_START_STREAM_ID 0x4200
677 #define FS4_RAID_MSI_DEVICE_ID 0x4300
678
679 #define FS6_PKI_AXI_SLAVE_NS \
680 (NIC400_FS_NOC_ROOT + NIC400_FS_NOC_SECURITY2_OFFSET)
681
682 #define FS6_PKI_AE_DME_APB_NS \
683 (NIC400_FS_NOC_ROOT + NIC400_FS_NOC_SECURITY7_OFFSET)
684 #define FS6_PKI_IDM_IO_CONTROL_DIRECT 0x0
685 #define FS6_PKI_IDM_RESET_CONTROL 0x0
686 #define FS6_PKI_RING_COUNT 32
687 #define FS6_PKI_DME_COUNT 1
688 #define FS6_PKI_AE_COUNT 4
689 #define FS6_PKI_START_STREAM_ID 0x4000
690 #define FS6_PKI_MSI_DEVICE_ID 0x4100
691
brcm_stingray_security_init(void)692 static void brcm_stingray_security_init(void)
693 {
694 unsigned int val;
695
696 val = mmio_read_32(SCR_GPV_SMMU_NS);
697 val |= BIT(0); /* SMMU NS = 1 */
698 mmio_write_32(SCR_GPV_SMMU_NS, val);
699
700 val = mmio_read_32(SCR_GPV_GIC500_NS);
701 val |= BIT(0); /* GIC-500 NS = 1 */
702 mmio_write_32(SCR_GPV_GIC500_NS, val);
703
704 val = mmio_read_32(HSLS_GPV_NOR_S0_NS);
705 val |= BIT(0); /* NOR SLAVE NS = 1 */
706 mmio_write_32(HSLS_GPV_NOR_S0_NS, val);
707
708 val = mmio_read_32(HSLS_GPV_IDM1_NS);
709 val |= BIT(0); /* DMA IDM NS = 1 */
710 val |= BIT(1); /* I2S IDM NS = 1 */
711 val |= BIT(2); /* AMAC IDM NS = 1 */
712 val |= BIT(3); /* SDIO0 IDM NS = 1 */
713 val |= BIT(4); /* SDIO1 IDM NS = 1 */
714 val |= BIT(5); /* DS_3 IDM NS = 1 */
715 mmio_write_32(HSLS_GPV_IDM1_NS, val);
716
717 val = mmio_read_32(HSLS_GPV_IDM2_NS);
718 val |= BIT(2); /* QSPI IDM NS = 1 */
719 val |= BIT(1); /* NOR IDM NS = 1 */
720 val |= BIT(0); /* NAND IDM NS = 1 */
721 mmio_write_32(HSLS_GPV_IDM2_NS, val);
722
723 val = mmio_read_32(HSLS_GPV_APBY_NS);
724 val |= BIT(10); /* I2S NS = 1 */
725 val |= BIT(4); /* IOPAD NS = 1 */
726 val |= 0xf; /* UARTx NS = 1 */
727 mmio_write_32(HSLS_GPV_APBY_NS, val);
728
729 val = mmio_read_32(HSLS_GPV_APBZ_NS);
730 val |= BIT(2); /* RNG NS = 1 */
731 mmio_write_32(HSLS_GPV_APBZ_NS, val);
732
733 val = mmio_read_32(HSLS_GPV_APBS_NS);
734 val |= 0x3; /* SPIx NS = 1 */
735 mmio_write_32(HSLS_GPV_APBS_NS, val);
736
737 val = mmio_read_32(HSLS_GPV_APBR_NS);
738 val |= BIT(7); /* QSPI APB NS = 1 */
739 val |= BIT(6); /* NAND APB NS = 1 */
740 val |= BIT(5); /* NOR APB NS = 1 */
741 val |= BIT(4); /* AMAC APB NS = 1 */
742 val |= BIT(1); /* DMA S1 APB NS = 1 */
743 mmio_write_32(HSLS_GPV_APBR_NS, val);
744
745 val = mmio_read_32(HSLS_SDIO0_SLAVE_NS);
746 val |= BIT(0); /* SDIO0 NS = 1 */
747 mmio_write_32(HSLS_SDIO0_SLAVE_NS, val);
748
749 val = mmio_read_32(HSLS_SDIO1_SLAVE_NS);
750 val |= BIT(0); /* SDIO1 NS = 1 */
751 mmio_write_32(HSLS_SDIO1_SLAVE_NS, val);
752
753 val = mmio_read_32(HSLS_GPV_APBX_NS);
754 val |= BIT(14); /* SMBUS1 NS = 1 */
755 val |= BIT(13); /* GPIO NS = 1 */
756 val |= BIT(12); /* WDT NS = 1 */
757 val |= BIT(11); /* SMBUS0 NS = 1 */
758 val |= BIT(10); /* Timer7 NS = 1 */
759 val |= BIT(9); /* Timer6 NS = 1 */
760 val |= BIT(8); /* Timer5 NS = 1 */
761 val |= BIT(7); /* Timer4 NS = 1 */
762 val |= BIT(6); /* Timer3 NS = 1 */
763 val |= BIT(5); /* Timer2 NS = 1 */
764 val |= BIT(4); /* Timer1 NS = 1 */
765 val |= BIT(3); /* Timer0 NS = 1 */
766 val |= BIT(2); /* MDIO NS = 1 */
767 val |= BIT(1); /* PWM NS = 1 */
768 mmio_write_32(HSLS_GPV_APBX_NS, val);
769
770 val = mmio_read_32(HSLS_GPV_QSPI_S0_NS);
771 val |= BIT(0); /* QSPI NS = 1 */
772 mmio_write_32(HSLS_GPV_QSPI_S0_NS, val);
773
774 #ifdef USE_FS4
775 val = 0x1; /* FS4 Crypto rm_slave */
776 mmio_write_32(FS4_CRYPTO_GPV_RM_SLAVE_NS, val);
777 val = 0x1; /* FS4 Crypto apb_switch */
778 mmio_write_32(FS4_CRYPTO_GPV_APB_SWITCH_NS, val);
779
780 val = 0x1; /* FS4 Raid rm_slave */
781 mmio_write_32(FS4_RAID_GPV_RM_SLAVE_NS, val);
782 val = 0x1; /* FS4 Raid apb_switch */
783 mmio_write_32(FS4_RAID_GPV_APB_SWITCH_NS, val);
784
785 val = 0x1; /* FS4 Crypto IDM */
786 mmio_write_32(FS4_CRYPTO_IDM_NS, val);
787 val = 0x1; /* FS4 RAID IDM */
788 mmio_write_32(FS4_RAID_IDM_NS, val);
789 #endif
790
791 #ifdef BL31_CCN_NONSECURE
792 /* Enable non-secure access to CCN registers */
793 mmio_write_32(OLY_MN_REGISTERS_NODE0_SECURE_ACCESS, 0x1);
794 #endif
795
796 #ifdef DDR_CTRL_PHY_NONSECURE
797 mmio_write_32(SCR_NOC_DDR_REGISTER_ACCESS, 0x1);
798 #endif
799
800 paxc_mhb_ns_init();
801
802 /* unlock scr idm for non secure access */
803 mmio_write_32(SCR_NOC_SECURITY0, 0xffffffff);
804
805 INFO("security init done\r\n");
806 }
807
brcm_gpio_pad_ns_init(void)808 void brcm_gpio_pad_ns_init(void)
809 {
810 /* configure all GPIO pads for non secure world access*/
811 mmio_write_32(GPIO_S_CNTRL_REG, 0xffffffff); /* 128-140 gpio pads */
812 mmio_write_32(GPIO_S_CNTRL_REG + 0x4, 0xffffffff); /* 96-127 gpio pad */
813 mmio_write_32(GPIO_S_CNTRL_REG + 0x8, 0xffffffff); /* 64-95 gpio pad */
814 mmio_write_32(GPIO_S_CNTRL_REG + 0xc, 0xffffffff); /* 32-63 gpio pad */
815 mmio_write_32(GPIO_S_CNTRL_REG + 0x10, 0xffffffff); /* 0-31 gpio pad */
816 }
817
818 #ifndef USE_DDR
brcm_stingray_sram_ns_init(void)819 static void brcm_stingray_sram_ns_init(void)
820 {
821 uintptr_t sram_root = TZC400_FS_SRAM_ROOT;
822 uintptr_t noc_root = NIC400_FS_NOC_ROOT;
823
824 mmio_write_32(sram_root + GATE_KEEPER_OFFSET, 1);
825 mmio_write_32(sram_root + REGION_ATTRIBUTES_0_OFFSET, 0xc0000000);
826 mmio_write_32(sram_root + REGION_ID_ACCESS_0_OFFSET, 0x00010001);
827 mmio_write_32(noc_root + NIC400_FS_NOC_SECURITY4_OFFSET, 0x1);
828 INFO(" stingray sram ns init done.\n");
829 }
830 #endif
831
ccn_pre_init(void)832 static void ccn_pre_init(void)
833 {
834 /*
835 * Set WFC bit of RN-I nodes where FS4 is connected.
836 * This is required inorder to wait for read/write requests
837 * completion acknowledgment. Otherwise FS4 Ring Manager is
838 * getting stale data because of re-ordering of read/write
839 * requests at CCN level
840 */
841 mmio_setbits_32(OLY_RNI3PDVM_REGISTERS_NODE8_AUX_CTL,
842 OLY_RNI3PDVM_REGISTERS_NODE8_AUX_CTL_WFC);
843 }
844
ccn_post_init(void)845 static void ccn_post_init(void)
846 {
847 mmio_setbits_32(OLY_HNI_REGISTERS_NODE0_PCIERC_RNI_NODEID_LIST,
848 SRP_RNI_PCIE_CONNECTED);
849 mmio_setbits_32(OLY_HNI_REGISTERS_NODE0_SA_AUX_CTL,
850 SA_AUX_CTL_SER_DEVNE_WR);
851
852 mmio_clrbits_32(OLY_HNI_REGISTERS_NODE0_POS_CONTROL,
853 POS_CONTROL_HNI_POS_EN);
854 mmio_clrbits_32(OLY_HNI_REGISTERS_NODE0_SA_AUX_CTL,
855 SA_AUX_CTL_POS_EARLY_WR_COMP_EN);
856 }
857
858 #ifndef BL31_BOOT_PRELOADED_SCP
crmu_init(void)859 static void crmu_init(void)
860 {
861 /*
862 * Configure CRMU for using SMMU
863 */
864
865 /*Program CRMU Stream ID */
866 mmio_write_32(CRMU_MASTER_AXI_ARUSER_CONFIG,
867 (CRMU_STREAM_ID << CRMU_SID_SHIFT));
868 mmio_write_32(CRMU_MASTER_AXI_AWUSER_CONFIG,
869 (CRMU_STREAM_ID << CRMU_SID_SHIFT));
870
871 /* Create Identity mapping */
872 arm_smmu_create_identity_map(DOMAIN_CRMU);
873
874 /* Enable Client Port for Secure Masters*/
875 arm_smmu_enable_secure_client_port();
876 }
877 #endif
878
brcm_fsx_init(void)879 static void brcm_fsx_init(void)
880 {
881 #if defined(USE_FS4) && defined(USE_FS6)
882 #error "USE_FS4 and USE_FS6 should not be used together"
883 #endif
884
885 #ifdef USE_FS4
886 fsx_init(eFS4_CRYPTO, FS4_CRYPTO_RING_COUNT, FS4_CRYPTO_DME_COUNT,
887 FS4_CRYPTO_AE_COUNT, FS4_CRYPTO_START_STREAM_ID,
888 FS4_CRYPTO_MSI_DEVICE_ID, FS4_CRYPTO_IDM_IO_CONTROL_DIRECT,
889 FS4_CRYPTO_IDM_RESET_CONTROL, FS4_CRYPTO_BASE,
890 FS4_CRYPTO_DME_BASE);
891
892 fsx_init(eFS4_RAID, FS4_RAID_RING_COUNT, FS4_RAID_DME_COUNT,
893 FS4_RAID_AE_COUNT, FS4_RAID_START_STREAM_ID,
894 FS4_RAID_MSI_DEVICE_ID, FS4_RAID_IDM_IO_CONTROL_DIRECT,
895 FS4_RAID_IDM_RESET_CONTROL, FS4_RAID_BASE,
896 FS4_RAID_DME_BASE);
897
898 fsx_meminit("raid",
899 FS4_RAID_IDM_IO_CONTROL_DIRECT,
900 FS4_RAID_IDM_IO_STATUS);
901 #endif
902 }
903
bcm_bl33_pass_info(void)904 static void bcm_bl33_pass_info(void)
905 {
906 struct bl33_info *info = (struct bl33_info *)BL33_SHARED_DDR_BASE;
907
908 if (sizeof(*info) > BL33_SHARED_DDR_SIZE)
909 WARN("bl33 shared area not reserved\n");
910
911 info->version = BL33_INFO_VERSION;
912 info->chip.chip_id = PLAT_CHIP_ID_GET;
913 info->chip.rev_id = PLAT_CHIP_REV_GET;
914 }
915
DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1,CORTEX_A72_L2CTLR_EL1)916 DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A72_L2CTLR_EL1)
917
918 void plat_bcm_bl31_early_platform_setup(void *from_bl2,
919 bl_params_t *plat_params_from_bl2)
920 {
921 #ifdef BL31_BOOT_PRELOADED_SCP
922 image_info_t scp_image_info;
923
924 scp_image_info.image_base = PRELOADED_SCP_BASE;
925 scp_image_info.image_size = PRELOADED_SCP_SIZE;
926 plat_bcm_bl2_plat_handle_scp_bl2(&scp_image_info);
927 #endif
928 /*
929 * In BL31, logs are saved to DDR and we have much larger space to
930 * store logs. We can now afford to save all logs >= the 'INFO' level
931 */
932 bcm_elog_init((void *)BCM_ELOG_BL31_BASE, BCM_ELOG_BL31_SIZE,
933 LOG_LEVEL_INFO);
934
935 INFO("L2CTLR = 0x%lx\n", read_l2ctlr_el1());
936
937 brcm_timer_sync_init();
938
939 brcm_stingray_dma_pl330_init();
940
941 brcm_stingray_dma_pl330_meminit();
942
943 brcm_stingray_spi_pl022_init(APBS_IDM_IDM_RESET_CONTROL);
944
945 #ifdef USE_AMAC
946 brcm_stingray_amac_init();
947 #endif
948
949 brcm_stingray_sdio_init();
950
951 #ifdef NCSI_IO_DRIVE_STRENGTH_MA
952 brcm_stingray_ncsi_init();
953 #endif
954
955 #ifdef USE_USB
956 xhci_phy_init();
957 #endif
958
959 #ifdef USE_SATA
960 brcm_stingray_sata_init();
961 #else
962 poweroff_sata_pll();
963 #endif
964
965 ccn_pre_init();
966
967 brcm_fsx_init();
968
969 brcm_stingray_smmu_init();
970
971 brcm_stingray_pka_meminit();
972
973 brcm_stingray_crmu_access_init();
974
975 brcm_stingray_scr_init();
976
977 brcm_stingray_hsls_tzpcprot_init();
978
979 #ifdef USE_I2S
980 brcm_stingray_audio_init();
981 #endif
982
983 ccn_post_init();
984
985 paxb_init();
986
987 paxc_init();
988
989 #ifndef BL31_BOOT_PRELOADED_SCP
990 crmu_init();
991 #endif
992
993 /* Note: this should be last thing because
994 * FS4 GPV registers only work after FS4 block
995 * (i.e. crypto,raid,cop) is out of reset.
996 */
997 brcm_stingray_security_init();
998
999 brcm_gpio_pad_ns_init();
1000
1001 #ifndef USE_DDR
1002 brcm_stingray_sram_ns_init();
1003 #endif
1004
1005 #ifdef BL31_FORCE_CPU_FULL_FREQ
1006 bcm_set_ihost_pll_freq(0x0, PLL_FREQ_FULL);
1007 #endif
1008
1009 brcm_stingray_gain_qspi_control();
1010
1011 #ifdef USE_PAXC
1012 /*
1013 * Check that the handshake has occurred and report ChiMP status.
1014 * This is required. Otherwise (especially on Palladium)
1015 * Linux might have booted to the pcie stage whereas
1016 * ChiMP has not yet booted. Note that nic_mode case has already
1017 * been considered above.
1018 */
1019 if ((boot_source_get() != BOOT_SOURCE_QSPI) &&
1020 (!bcm_chimp_is_nic_mode()) &&
1021 (!bcm_chimp_wait_handshake())
1022 ) {
1023 /* Does ChiMP report an error ? */
1024 uint32_t err;
1025
1026 err = bcm_chimp_read_ctrl(CHIMP_REG_CTRL_BPE_STAT_REG);
1027 if ((err & CHIMP_ERROR_MASK) == 0)
1028 /* ChiMP has not booted yet, but no error reported */
1029 WARN("ChiMP not booted yet, but no error reported.\n");
1030 }
1031
1032 #if DEBUG
1033 if (boot_source_get() != BOOT_SOURCE_QSPI)
1034 INFO("Current ChiMP Status: 0x%x; bpe_mod reg: 0x%x\n"
1035 "fastboot register: 0x%x; handshake register 0x%x\n",
1036 bcm_chimp_read_ctrl(CHIMP_REG_CTRL_BPE_STAT_REG),
1037 bcm_chimp_read_ctrl(CHIMP_REG_CTRL_BPE_MODE_REG),
1038 bcm_chimp_read_ctrl(CHIMP_REG_CTRL_FSTBOOT_PTR_REG),
1039 bcm_chimp_read(CHIMP_REG_ECO_RESERVED));
1040 #endif /* DEBUG */
1041 #endif
1042
1043 #ifdef FS4_DISABLE_CLOCK
1044 flush_dcache_range(
1045 PLAT_BRCM_TRUSTED_SRAM_BASE,
1046 PLAT_BRCM_TRUSTED_SRAM_SIZE);
1047 fs4_disable_clocks(true, true, true);
1048 #endif
1049
1050 /* pass information to BL33 through shared DDR region */
1051 bcm_bl33_pass_info();
1052
1053 /*
1054 * We are not yet at the end of BL31, but we can stop log here so we do
1055 * not need to add 'bcm_elog_exit' to the standard BL31 code. The
1056 * benefit of capturing BL31 logs after this is very minimal in a
1057 * production system
1058 */
1059 bcm_elog_exit();
1060
1061 #if !BRCM_DISABLE_TRUSTED_WDOG
1062 /*
1063 * Secure watchdog was started earlier in BL2, now it's time to stop
1064 * it
1065 */
1066 sp805_stop(ARM_SP805_TWDG_BASE);
1067 #endif
1068 }
1069