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Searched refs:DMODU (Results 1 – 20 of 20) sorted by relevance

/external/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td112 def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
DMipsISelLowering.cpp1067 case Mips::DMODU: in EmitInstrWithCustomInserter()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td144 def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
DMipsScheduleGeneric.td269 def : InstRW<[GenericWriteDIVU], (instrs DDIVU, DMODU)>;
DMipsISelLowering.cpp1430 case Mips::DMODU: in EmitInstrWithCustomInserter()
/external/llvm-project/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td144 def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
DMipsScheduleGeneric.td269 def : InstRW<[GenericWriteDIVU], (instrs DDIVU, DMODU)>;
DMipsISelLowering.cpp1420 case Mips::DMODU: in EmitInstrWithCustomInserter()
/external/pcre/dist2/src/sljit/
DsljitNativeMIPS_common.c173 #define DMODU (HI(0) | (3 << 6) | LO(31)) macro
1270 …FAIL_IF(push_inst(compiler, ((op | 0x2) == SLJIT_DIV_UW ? DMODU : DMOD) | S(SLJIT_R0) | T(SLJIT_R1… in sljit_emit_op0()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc1170 {DBGFIELD("DMODU") 1, false, false, 34, 2, 12, 1, 0, 0}, // #910
2854 {DBGFIELD("DMODU") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #910
DMipsGenMCCodeEmitter.inc1336 UINT64_C(223), // DMODU
5021 case Mips::DMODU:
10798 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMODU = 1323
DMipsGenAsmWriter.inc2564 268459619U, // DMODU
5318 0U, // DMODU
DMipsGenFastISel.inc2687 return fastEmitInst_rr(Mips::DMODU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
DMipsGenInstrInfo.inc1338 DMODU = 1323,
3690 DMODU = 910,
6184 …UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1323 = DMODU
DMipsGenDisassemblerTables.inc6339 /* 488 */ MCD::OPC_Decode, 171, 10, 12, // Opcode: DMODU
DMipsGenAsmMatcher.inc6386 …{ 3357 /* dmodu */, Mips::DMODU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_Ha…
DMipsGenGlobalISel.inc2095 …// (urem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMODU:{ *:[i64] }…
2096 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMODU,
DMipsGenDAGISel.inc26788 /* 50687*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DMODU), 0,
26791 // Dst: (DMODU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc601 134241281U, // DMODU
2390 0U, // DMODU
DMipsGenDisassemblerTables.inc3928 /* 427 */ MCD_OPC_Decode, 200, 4, 224, 1, // Opcode: DMODU