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Searched refs:DMUH (Results 1 – 18 of 18) sorted by relevance

/external/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td116 def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td146 def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
DMipsScheduleGeneric.td265 def : InstRW<[GenericWriteMDUtoGPR], (instrs DMUH, DMUHU, DMUL_R6)>;
/external/llvm-project/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td146 def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
DMipsScheduleGeneric.td265 def : InstRW<[GenericWriteMDUtoGPR], (instrs DMUH, DMUHU, DMUL_R6)>;
/external/pcre/dist2/src/sljit/
DsljitNativeMIPS_64.c477 …FAIL_IF(push_inst(compiler, SELECT_OP(DMUH, MUH) | S(src1) | T(src2) | DA(EQUAL_FLAG), EQUAL_FLAG)… in emit_single_op()
DsljitNativeMIPS_common.c176 #define DMUH (HI(0) | (3 << 6) | LO(28)) macro
1241 …FAIL_IF(push_inst(compiler, (op == SLJIT_LMUL_UW ? DMUHU : DMUH) | S(SLJIT_R0) | T(SLJIT_R1) | D(T… in sljit_emit_op0()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc1164 {DBGFIELD("DMUH") 1, false, false, 12, 2, 5, 1, 0, 0}, // #904
2848 {DBGFIELD("DMUH") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #904
DMipsGenMCCodeEmitter.inc1343 UINT64_C(220), // DMUH
5022 case Mips::DMUH:
10805 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUH = 1330
DMipsGenAsmWriter.inc2571 268457787U, // DMUH
5325 0U, // DMUH
DMipsGenFastISel.inc1799 return fastEmitInst_rr(Mips::DMUH, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
DMipsGenInstrInfo.inc1345 DMUH = 1330,
3684 DMUH = 904,
6191 …330, 3, 1, 4, 904, 0, 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1330 = DMUH
DMipsGenDisassemblerTables.inc6315 /* 380 */ MCD::OPC_Decode, 178, 10, 12, // Opcode: DMUH
DMipsGenAsmMatcher.inc6397 …{ 3392 /* dmuh */, Mips::DMUH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasS…
DMipsGenGlobalISel.inc21505 …// (mulhs:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUH:{ *:[i64] }…
21506 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUH,
DMipsGenDAGISel.inc26040 /* 49299*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DMUH), 0,
26043 // Dst: (DMUH:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc605 134239671U, // DMUH
2394 0U, // DMUH
DMipsGenDisassemblerTables.inc3904 /* 328 */ MCD_OPC_Decode, 204, 4, 224, 1, // Opcode: DMUH