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Searched refs:DMUHU (Results 1 – 17 of 17) sorted by relevance

/external/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td117 def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td147 def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
DMipsScheduleGeneric.td265 def : InstRW<[GenericWriteMDUtoGPR], (instrs DMUH, DMUHU, DMUL_R6)>;
/external/llvm-project/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td147 def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
DMipsScheduleGeneric.td265 def : InstRW<[GenericWriteMDUtoGPR], (instrs DMUH, DMUHU, DMUL_R6)>;
/external/pcre/dist2/src/sljit/
DsljitNativeMIPS_common.c177 #define DMUHU (HI(0) | (3 << 6) | LO(29)) macro
1241 …FAIL_IF(push_inst(compiler, (op == SLJIT_LMUL_UW ? DMUHU : DMUH) | S(SLJIT_R0) | T(SLJIT_R1) | D(T… in sljit_emit_op0()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc1165 {DBGFIELD("DMUHU") 1, false, false, 12, 2, 5, 1, 0, 0}, // #905
2849 {DBGFIELD("DMUHU") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #905
DMipsGenMCCodeEmitter.inc1344 UINT64_C(221), // DMUHU
5023 case Mips::DMUHU:
10806 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUHU = 1331
DMipsGenAsmWriter.inc2572 268459656U, // DMUHU
5326 0U, // DMUHU
DMipsGenFastISel.inc1830 return fastEmitInst_rr(Mips::DMUHU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
DMipsGenInstrInfo.inc1346 DMUHU = 1331,
3685 DMUHU = 905,
6192 …31, 3, 1, 4, 905, 0, 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1331 = DMUHU
DMipsGenDisassemblerTables.inc6323 /* 416 */ MCD::OPC_Decode, 179, 10, 12, // Opcode: DMUHU
DMipsGenAsmMatcher.inc6398 …{ 3397 /* dmuhu */, Mips::DMUHU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_Ha…
DMipsGenGlobalISel.inc21458 …// (mulhu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUHU:{ *:[i64] …
21459 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUHU,
DMipsGenDAGISel.inc26064 /* 49344*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DMUHU), 0,
26067 // Dst: (DMUHU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc606 134241299U, // DMUHU
2395 0U, // DMUHU
DMipsGenDisassemblerTables.inc3912 /* 361 */ MCD_OPC_Decode, 205, 4, 224, 1, // Opcode: DMUHU