Searched refs:DMULU (Results 1 – 14 of 14) sorted by relevance
| /external/llvm/lib/Target/Mips/ |
| D | Mips64r6InstrInfo.td | 119 def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | Mips64r6InstrInfo.td | 149 def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
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| D | MipsScheduleGeneric.td | 245 def : InstRW<[GenericWriteHILO], (instrs DMULU, DMULT, DMULTu, PseudoDMULT,
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | Mips64r6InstrInfo.td | 149 def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
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| D | MipsScheduleGeneric.td | 245 def : InstRW<[GenericWriteHILO], (instrs DMULU, DMULT, DMULTu, PseudoDMULT,
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_common.c | 179 #define DMULU (HI(0) | (2 << 6) | LO(29)) macro
1240 …FAIL_IF(push_inst(compiler, (op == SLJIT_LMUL_UW ? DMULU : DMUL) | S(SLJIT_R0) | T(SLJIT_R1) | D(T… in sljit_emit_op0()
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 1153 {DBGFIELD("DMULU") 1, false, false, 12, 2, 1, 1, 0, 0}, // #893
2837 {DBGFIELD("DMULU") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #893
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| D | MipsGenMCCodeEmitter.inc | 1348 UINT64_C(157), // DMULU
5025 case Mips::DMULU:
10810 CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMULU = 1335
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| D | MipsGenAsmWriter.inc | 2576 268459700U, // DMULU
5330 0U, // DMULU
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| D | MipsGenInstrInfo.inc | 1350 DMULU = 1335,
3673 DMULU = 893,
6196 …modeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1335 = DMULU
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| D | MipsGenDisassemblerTables.inc | 6320 /* 402 */ MCD::OPC_Decode, 183, 10, 12, // Opcode: DMULU
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| D | MipsGenAsmMatcher.inc | 6408 …{ 3434 /* dmulu */, Mips::DMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_Ha…
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 610 134241343U, // DMULU
2399 0U, // DMULU
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| D | MipsGenDisassemblerTables.inc | 3909 /* 348 */ MCD_OPC_Decode, 209, 4, 224, 1, // Opcode: DMULU
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