| /external/wpa_supplicant_8/wpa_supplicant/ |
| D | README-DPP | 1 Device Provisioning Protocol (DPP)
4 This document describes how the Device Provisioning Protocol (DPP)
6 the STA device and AP can be configured to connect each other using DPP
9 Introduction to DPP
15 authentication (password with in-band provisioning), etc. In DPP a
17 three phases of DPP connection are authentication, configuration and
33 Enable DPP in wpa_supplicant build config file
40 Enable DPP in hostapd build config file
47 Any STA or AP device can act as a Configurator. Enable DPP in build
72 wpa_key_mgmt=DPP
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | dpp_combine.mir | 5 # bound_ctrl:0 is set, otherwise the result of DPP VALU op can be undefined.
60 # the DPP mov result would be either zero ({src lane disabled}|{src lane is
67 # as the DPP mov old is zero this case is no different from case 1 - combine it
68 # setting bound_ctrl0 on for the combined DPP VALU op to make old undefined
73 # the DPP mov result would be either zero ({src lane disabled}|{src lane is
74 # out of range} or {the DPP mov's dest VGPR write is disabled by masks}) or
76 # The VALU op should have the same masks as DPP mov as they select lanes
78 # Special case: the bound_ctrl for the combined DPP VALU op isn't important
83 # the DPP mov result would be either zero ({src lane disabled}|{src lane is
84 # out of range} or {the DPP mov's dest VGPR write is disabled by masks}) or
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUAtomicOptimizer.cpp | 298 {Identity, V, B.getInt32(DPP::ROW_SHR0 | 1 << Idx), in buildScan()
306 {Identity, V, B.getInt32(DPP::BCAST15), B.getInt32(0xa), in buildScan()
311 {Identity, V, B.getInt32(DPP::BCAST31), B.getInt32(0xc), in buildScan()
325 {Identity, PermX, B.getInt32(DPP::QUAD_PERM_ID), in buildScan()
333 {Identity, Lane31, B.getInt32(DPP::QUAD_PERM_ID), in buildScan()
356 {Identity, V, B.getInt32(DPP::WAVE_SHR1), B.getInt32(0xf), in buildShiftRight()
363 {Identity, V, B.getInt32(DPP::ROW_SHR0 + 1), in buildShiftRight()
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| D | VOPInstructions.td | 618 let DPP = 1;
633 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP,
637 let DecoderNamespace = "DPP";
682 let DPP = 1;
688 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP,
692 let DecoderNamespace = "DPP";
714 let DPP = 1;
720 let AsmVariantName = !if(P.HasExt, AMDGPUAsmVariants.DPP,
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| D | SIDefines.h | 42 DPP = 1 << 15, enumerator
237 DPP = 4 enumerator
641 namespace DPP {
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| D | GCNHazardRecognizer.h | 76 int checkDPPHazards(MachineInstr *DPP);
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| D | SIInstrFormats.td | 35 field bit DPP = 0;
156 let TSFlags{15} = DPP;
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| D | AMDGPU.td | 380 "Support DPP (Data Parallel Primitives) extension"
1015 string DPP = "DPP";
1044 let Name = AMDGPUAsmVariants.DPP;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUAtomicOptimizer.cpp | 298 {Identity, V, B.getInt32(DPP::ROW_SHR0 | 1 << Idx), in buildScan()
306 {Identity, V, B.getInt32(DPP::BCAST15), B.getInt32(0xa), in buildScan()
311 {Identity, V, B.getInt32(DPP::BCAST31), B.getInt32(0xc), in buildScan()
325 {Identity, PermX, B.getInt32(DPP::QUAD_PERM_ID), in buildScan()
333 {Identity, Lane31, B.getInt32(DPP::QUAD_PERM_ID), in buildScan()
356 {Identity, V, B.getInt32(DPP::WAVE_SHR1), B.getInt32(0xf), in buildShiftRight()
363 {Identity, V, B.getInt32(DPP::ROW_SHR0 + 1), in buildShiftRight()
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| D | SIDefines.h | 42 DPP = 1 << 15, enumerator
232 DPP = 4 enumerator
446 namespace DPP {
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| D | VOPInstructions.td | 608 let DPP = 1;
619 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP,
623 let DecoderNamespace = "DPP";
668 let DPP = 1;
674 let AsmVariantName = !if(P.HasExtDPP, AMDGPUAsmVariants.DPP,
678 let DecoderNamespace = "DPP";
700 let DPP = 1;
706 let AsmVariantName = !if(P.HasExt, AMDGPUAsmVariants.DPP,
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| D | GCNHazardRecognizer.h | 76 int checkDPPHazards(MachineInstr *DPP);
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| D | SIInstrFormats.td | 35 field bit DPP = 0;
148 let TSFlags{15} = DPP;
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| D | AMDGPU.td | 350 "Support DPP (Data Parallel Primitives) extension"
921 string DPP = "DPP";
950 let Name = AMDGPUAsmVariants.DPP;
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| /external/llvm/lib/Target/AMDGPU/ |
| D | GCNHazardRecognizer.cpp | 248 int GCNHazardRecognizer::checkDPPHazards(MachineInstr *DPP) { in checkDPPHazards() argument
255 for (const MachineOperand &Use : DPP->uses()) { in checkDPPHazards()
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| D | GCNHazardRecognizer.h | 45 int checkDPPHazards(MachineInstr *DPP);
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| D | SIDefines.h | 33 DPP = 1 << 15, enumerator
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| D | SIInstrInfo.h | 352 return MI.getDesc().TSFlags & SIInstrFlags::DPP; in isDPP()
356 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
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| D | VIInstructions.td | 128 // DPP Patterns
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| D | VIInstrFormats.td | 182 let DPP = 1;
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| D | SIInstrFormats.td | 36 field bits<1> DPP = 0;
72 let TSFlags{15} = DPP;
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| /external/llvm-project/llvm/docs/ |
| D | AMDGPUInstructionSyntax.rst | 126 they may also be encoded in *VOP3*, *DPP* and *SDWA* formats.
136 *DPP* encoding _dpp
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| /external/ImageMagick/PerlMagick/t/ |
| D | input_gray_lsb_08bit.mat | 3 …E@UNIEFB+ L?GDA@B?>;899529>>=?>>?A?93.* 31JazpGKKKKMNNMMOOOPPNNMKIHEIA)??DPP^E'-EACGC@GFA?A>975…
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| /external/mesa3d/src/amd/compiler/ |
| D | aco_opcodes.py | 59 DPP = 1 << 13 variable in Format
132 elif self == Format.DPP:
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | AMDGPUInstPrinter.cpp | 308 else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::DPP) in printVOPDst()
699 using namespace AMDGPU::DPP; in printDPPCtrl()
807 using namespace llvm::AMDGPU::DPP; in printFI()
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