| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_64.c | 85 ins = (shift == 32) ? DSLL32 : DSLL; in load_immediate()
179 FAIL_IF(push_inst(compiler, DSLL32 | T(src2) | D(dst) | SH_IMM(24), DR(dst))); in emit_single_op()
194 FAIL_IF(push_inst(compiler, DSLL32 | T(src2) | D(dst) | SH_IMM(16), DR(dst))); in emit_single_op()
206 FAIL_IF(push_inst(compiler, DSLL32 | T(src2) | D(dst) | SH_IMM(0), DR(dst))); in emit_single_op()
290 …FAIL_IF(push_inst(compiler, SELECT_OP(DSLL32, SLL) | TA(OTHER_FLAG) | D(TMP_REG1) | SH_IMM(31), DR… in emit_single_op()
423 …FAIL_IF(push_inst(compiler, SELECT_OP(DSLL32, SLL) | TA(OTHER_FLAG) | D(TMP_REG1) | SH_IMM(31), DR… in emit_single_op()
499 EMIT_SHIFT(DSLL, DSLL32, SLL, DSLLV, SLLV); in emit_single_op()
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| D | sljitNativeMIPS_common.c | 190 #define DSLL32 (HI(0) | LO(60)) macro
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 2499 TOut.emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, STI); in loadAndAddSymbolAddress()
3111 TOut.emitRRI(Mips::DSLL32, ATReg, ATReg, 0x1f, IDLoc, STI); in expandDiv()
3633 FirstShift = Mips::DSLL32; in expandDRotationImm()
3637 FirstShift = Mips::DSLL32; in expandDRotationImm()
3644 SecondShift = Mips::DSLL32; in expandDRotationImm()
3648 SecondShift = Mips::DSLL32; in expandDRotationImm()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 70 Inst.setOpcode(Mips::DSLL32); in LowerLargeShift()
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| D | MipsTargetStreamer.cpp | 203 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI); in emitDSLL()
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| /external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 77 Inst.setOpcode(Mips::DSLL32); in LowerLargeShift()
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| D | MipsTargetStreamer.cpp | 271 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI); in emitDSLL()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 77 Inst.setOpcode(Mips::DSLL32); in LowerLargeShift()
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| D | MipsTargetStreamer.cpp | 268 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI); in emitDSLL()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.cpp | 1239 Mips::DSLL32, DL, MVT::i64, SDValue(HiRes, 0), in trySelect()
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| D | Mips64InstrInfo.td | 182 def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
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| D | MipsScheduleGeneric.td | 127 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL,
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.cpp | 1312 Mips::DSLL32, DL, MVT::i64, SDValue(HiRes, 0), in trySelect()
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| D | Mips64InstrInfo.td | 182 def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
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| D | MipsScheduleGeneric.td | 127 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL,
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| /external/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3145 TOut.emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, STI); in loadAndAddSymbolAddress()
5099 FirstShift = Mips::DSLL32; in expandDRotationImm()
5103 FirstShift = Mips::DSLL32; in expandDRotationImm()
5110 SecondShift = Mips::DSLL32; in expandDRotationImm()
5114 SecondShift = Mips::DSLL32; in expandDRotationImm()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3117 TOut.emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, STI); in loadAndAddSymbolAddress()
4989 FirstShift = Mips::DSLL32; in expandDRotationImm()
4993 FirstShift = Mips::DSLL32; in expandDRotationImm()
5000 SecondShift = Mips::DSLL32; in expandDRotationImm()
5004 SecondShift = Mips::DSLL32; in expandDRotationImm()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 155 def DSLL32 : StdMMR6Rel, shift_rotate_imm<"dsll32", uimm5, GPR64Opnd,
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 1082 {DBGFIELD("DSLL32") 1, false, false, 1, 2, 1, 1, 0, 0}, // #822
2766 {DBGFIELD("DSLL32") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #822
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| D | MipsGenMCCodeEmitter.inc | 1408 UINT64_C(60), // DSLL32
5334 case Mips::DSLL32:
10870 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL32 = 1395
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| D | MipsGenAsmWriter.inc | 2636 268452087U, // DSLL32
5390 4U, // DSLL32
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| D | MipsGenAsmMatcher.inc | 6492 …{ 3871 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AM…
6493 …{ 3871 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AM…
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| D | MipsGenInstrInfo.inc | 1410 DSLL32 = 1395,
3602 DSLL32 = 822,
6256 …odeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1395 = DSLL32
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 654 134234321U, // DSLL32
2443 1U, // DSLL32
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| D | MipsGenDisassemblerTables.inc | 4348 /* 318 */ MCD_OPC_Decode, 253, 4, 254, 1, // Opcode: DSLL32
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