| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandCondsets.cpp | 414 unsigned DR = Op.getReg(), DSR = Op.getSubReg(); in updateDeadsInRange() local
417 LaneBitmask SLM = getLaneMask(DR, DSR); in updateDeadsInRange()
655 unsigned DR = MD.getReg(), DSR = MD.getSubReg(); in split() local
659 if (ReadUndef && DSR != 0 && MRI->shouldTrackSubRegLiveness(DR)) { in split()
665 NewSR = (DSR == Hexagon::subreg_loreg) ? Hexagon::subreg_hireg in split()
687 genCondTfrFor(MI.getOperand(2), At, DR, DSR, MP, true, ReadUndef, false); in split()
689 genCondTfrFor(MI.getOperand(3), At, DR, DSR, MP, false, ReadUndef, true); in split()
|
| /external/libcups/templates/ja/ |
| D | choose-serial.tmpl | 40 <OPTION VALUE="dtrdsr" {?flow=dtrdsr?SELECTED:}>DTR/DSR (ハードウェア)
|
| /external/libcups/templates/ru/ |
| D | choose-serial.tmpl | 40 <OPTION VALUE="dtrdsr" {?flow=dtrdsr?SELECTED:}>DTR/DSR (Аппаратное)
|
| /external/libcups/templates/da/ |
| D | choose-serial.tmpl | 40 <OPTION VALUE="dtrdsr" {?flow=dtrdsr?SELECTED:}>DTR/DSR (hardware)
|
| /external/libcups/templates/ |
| D | choose-serial.tmpl | 40 <OPTION VALUE="dtrdsr" {?flow=dtrdsr?SELECTED:}>DTR/DSR (Hardware)
|
| /external/libcups/templates/de/ |
| D | choose-serial.tmpl | 40 <OPTION VALUE="dtrdsr" {?flow=dtrdsr?SELECTED:}>DTR/DSR (Hardware)
|
| /external/libcups/templates/pt_BR/ |
| D | choose-serial.tmpl | 40 <OPTION VALUE="dtrdsr" {?flow=dtrdsr?SELECTED:}>DTR/DSR (Hardware)
|
| /external/libcups/templates/es/ |
| D | choose-serial.tmpl | 40 <OPTION VALUE="dtrdsr" {?flow=dtrdsr?SELECTED:}>DTR/DSR (Hardware)
|
| /external/libcups/templates/fr/ |
| D | choose-serial.tmpl | 40 <OPTION VALUE="dtrdsr" {?flow=dtrdsr?SELECTED:}>DTR/DSR (Matériel)
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandCondsets.cpp | 377 Register DR = Op.getReg(), DSR = Op.getSubReg(); in updateDeadsInRange() local
380 LaneBitmask SLM = getLaneMask(DR, DSR); in updateDeadsInRange()
676 Register DR = MD.getReg(), DSR = MD.getSubReg(); in split() local
710 genCondTfrFor(ST, At, DR, DSR, MP, true, ReadUndef, false); in split()
712 genCondTfrFor(SF, At, DR, DSR, MP, false, ReadUndef, true); in split()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandCondsets.cpp | 376 Register DR = Op.getReg(), DSR = Op.getSubReg(); in updateDeadsInRange() local
379 LaneBitmask SLM = getLaneMask(DR, DSR); in updateDeadsInRange()
675 Register DR = MD.getReg(), DSR = MD.getSubReg(); in split() local
709 genCondTfrFor(ST, At, DR, DSR, MP, true, ReadUndef, false); in split()
711 genCondTfrFor(SF, At, DR, DSR, MP, false, ReadUndef, true); in split()
|
| /external/clang/lib/Sema/ |
| D | SemaChecking.cpp | 6191 SourceRange DSR = Dest->getSourceRange(); in CheckMemaccessArguments() local
6198 DSR = SourceRange(SM.getSpellingLoc(DSR.getBegin()), in CheckMemaccessArguments()
6199 SM.getSpellingLoc(DSR.getEnd())); in CheckMemaccessArguments()
6209 << DSR in CheckMemaccessArguments()
|
| /external/llvm-project/clang/lib/Sema/ |
| D | SemaChecking.cpp | 9929 SourceRange DSR = Dest->getSourceRange(); in CheckMemaccessArguments() local
9936 DSR = SourceRange(SM.getSpellingLoc(DSR.getBegin()), in CheckMemaccessArguments()
9937 SM.getSpellingLoc(DSR.getEnd())); in CheckMemaccessArguments()
9947 << DSR in CheckMemaccessArguments()
|
| /external/cpuinfo/test/dmesg/ |
| D | zenfone-2.log | 1258 [ 4.049032] [drm] mdfld_dsi_dsr_init: Video mode panel, disabling DSR
|
| /external/cldr/tools/java/org/unicode/cldr/util/data/external/ |
| D | 2013-1_UNLOCODE_CodeListPart2.csv | 15825 ,"JP","DSR","Dohshiro","Dohshiro","42","1-------","AF","9907",,,
|
| D | 2013-1_UNLOCODE_CodeListPart1.csv | 8955 ,"CA","DSR","Deseronto","Deseronto","ON","-23-----","RL","0005",,"4411N 07701W",
41846 "+","FR","DSR","Saint-Restitut","Saint-Restitut","26","--3-----","RL","1301",,"4420N 00447E",
|
| D | 2013-1_UNLOCODE_CodeListPart3.csv | 13762 ,"US","DSR","Deshler","Deshler","NE","1-3--6--","RL","0607",,"4008N 09743W",
|
| /external/one-true-awk/testdir/ |
| D | funstack.in | 17018 @Article{Claudson:1975:DSR,
|