| /external/llvm-project/llvm/test/CodeGen/Mips/ |
| D | fcopysign-f32-f64.ll | 19 ; 64-DAG: dsrl $[[DSRL:[0-9]+]], ${{[0-9]+}}, 63
20 ; 64-DAG: sll $[[SLL0:[0-9]+]], $[[DSRL]], 0
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| /external/llvm/test/CodeGen/Mips/ |
| D | fcopysign-f32-f64.ll | 19 ; 64-DAG: dsrl $[[DSRL:[0-9]+]], ${{[0-9]+}}, 63
20 ; 64-DAG: sll $[[SLL0:[0-9]+]], $[[DSRL]], 0
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 72 case Mips::DSRL: in LowerLargeShift()
197 case Mips::DSRL: in encodeInstruction()
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| /external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 79 case Mips::DSRL: in LowerLargeShift()
165 case Mips::DSRL: in encodeInstruction()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 79 case Mips::DSRL: in LowerLargeShift()
165 case Mips::DSRL: in encodeInstruction()
|
| /external/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 143 def DSRL : StdMMR6Rel, shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL,
588 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_64.c | 503 EMIT_SHIFT(DSRL, DSRL32, SRL, DSRLV, SRLV); in emit_single_op()
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| D | sljitNativeMIPS_common.c | 195 #define DSRL (HI(0) | LO(58)) macro
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 170 def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl,
838 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>,
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| D | MipsScheduleGeneric.td | 127 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL,
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 170 def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl,
838 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>,
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| D | MipsScheduleGeneric.td | 127 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL,
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3620 TOut.emitRRI(Mips::DSRL, DReg, SReg, 0, Inst.getLoc(), STI); in expandDRotationImm()
3638 SecondShift = Mips::DSRL; in expandDRotationImm()
3643 FirstShift = Mips::DSRL; in expandDRotationImm()
|
| /external/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 5086 TOut.emitRRI(Mips::DSRL, DReg, SReg, 0, Inst.getLoc(), STI); in expandDRotationImm()
5104 SecondShift = Mips::DSRL; in expandDRotationImm()
5109 FirstShift = Mips::DSRL; in expandDRotationImm()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4976 TOut.emitRRI(Mips::DSRL, DReg, SReg, 0, Inst.getLoc(), STI); in expandDRotationImm()
4994 SecondShift = Mips::DSRL; in expandDRotationImm()
4999 FirstShift = Mips::DSRL; in expandDRotationImm()
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 1087 {DBGFIELD("DSRL") 1, false, false, 1, 2, 1, 1, 0, 0}, // #827
2771 {DBGFIELD("DSRL") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #827
|
| D | MipsGenMCCodeEmitter.inc | 1414 UINT64_C(58), // DSRL
5337 case Mips::DSRL:
10876 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL = 1401
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| D | MipsGenAsmWriter.inc | 2642 268458214U, // DSRL
5396 12U, // DSRL
|
| D | MipsGenFastISel.inc | 3771 return fastEmitInst_ri(Mips::DSRL, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
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| D | MipsGenAsmMatcher.inc | 6502 …{ 3902 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_…
6504 …{ 3902 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_…
|
| D | MipsGenGlobalISel.inc | 13082 …// (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DSRL:{ *:[i64] } (DSLL64_32:{ *:[i64] } GPR32:{…
13088 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRL,
14033 …:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSRL:{ *:[i64] } GPR64Op…
14034 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRL,
|
| D | MipsGenInstrInfo.inc | 1416 DSRL = 1401,
3607 DSRL = 827,
6262 …401, 3, 1, 4, 827, 0, 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1401 = DSRL
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| D | MipsGenDAGISel.inc | 15039 /* 27751*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSRL), 0,
15042 … // Dst: (DSRL:{ *:[i64] } (DSLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src), 32:{ *:[i32] })
20164 /* 37651*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSRL), 0,
20167 // Dst: (DSRL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
|
| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 660 134240069U, // DSRL
2449 1U, // DSRL
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| D | MipsGenDisassemblerTables.inc | 4337 /* 267 */ MCD_OPC_Decode, 131, 5, 254, 1, // Opcode: DSRL
|