| /external/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 153 def DSRLV : StdMMR6Rel, shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
577 (DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
696 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 180 def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
825 (DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>,
1023 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
1026 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rd, GPR32Opnd:$rt), 0>,
|
| D | MipsScheduleGeneric.td | 128 DSRL32, DSRLV, DSUB, DSUBu, LEA_ADDiu64,
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 180 def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
825 (DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>,
1023 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
1026 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rd, GPR32Opnd:$rt), 0>,
|
| D | MipsScheduleGeneric.td | 128 DSRL32, DSRLV, DSUB, DSUBu, LEA_ADDiu64,
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_64.c | 503 EMIT_SHIFT(DSRL, DSRL32, SRL, DSRLV, SRLV); in emit_single_op()
|
| D | sljitNativeMIPS_common.c | 197 #define DSRLV (HI(0) | LO(22)) macro
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3551 FirstShift = Mips::DSRLV; in expandDRotation()
3556 SecondShift = Mips::DSRLV; in expandDRotation()
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 1089 {DBGFIELD("DSRLV") 1, false, false, 1, 2, 1, 1, 0, 0}, // #829
2773 {DBGFIELD("DSRLV") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #829
|
| D | MipsGenMCCodeEmitter.inc | 1416 UINT64_C(22), // DSRLV
5270 case Mips::DSRLV:
10878 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRLV = 1403
|
| D | MipsGenAsmWriter.inc | 2644 268459896U, // DSRLV
5398 0U, // DSRLV
|
| D | MipsGenAsmMatcher.inc | 6501 …{ 3902 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, AMFBS_Has…
6503 …{ 3902 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_Has…
6507 …{ 3914 /* dsrlv */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_Ha…
|
| D | MipsGenGlobalISel.inc | 14050 …} GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRLV:{ *:[i64] } GPR64:…
14057 GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRLV,
14069 …// (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRLV:{ *:[i64] } …
14070 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSRLV,
|
| D | MipsGenInstrInfo.inc | 1418 DSRLV = 1403,
3609 DSRLV = 829,
6264 …3, 3, 1, 4, 829, 0, 0x1ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #1403 = DSRLV
|
| D | MipsGenDAGISel.inc | 20210 /* 37738*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSRLV), 0,
20213 …// Dst: (DSRLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$r…
20239 /* 37792*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSRLV), 0,
20242 // Dst: (DSRLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
|
| D | MipsGenDisassemblerTables.inc | 6884 /* 122 */ MCD::OPC_Decode, 251, 10, 238, 2, // Opcode: DSRLV
|
| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 662 134241482U, // DSRLV
2451 0U, // DSRLV
|
| D | MipsGenDisassemblerTables.inc | 4289 /* 44 */ MCD_OPC_Decode, 133, 5, 252, 1, // Opcode: DSRLV
|
| /external/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 5019 FirstShift = Mips::DSRLV; in expandDRotation()
5024 SecondShift = Mips::DSRLV; in expandDRotation()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4909 FirstShift = Mips::DSRLV; in expandDRotation()
4914 SecondShift = Mips::DSRLV; in expandDRotation()
|