| /external/llvm/include/llvm/MC/ |
| D | MCInstrItineraries.h | 186 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding() argument
190 if ((FirstDefIdx + DefIdx) >= LastDefIdx) in hasPipelineForwarding()
192 if (Forwardings[FirstDefIdx + DefIdx] == 0) in hasPipelineForwarding()
200 return Forwardings[FirstDefIdx + DefIdx] == in hasPipelineForwarding()
207 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency() argument
212 int DefCycle = getOperandCycle(DefClass, DefIdx); in getOperandLatency()
222 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
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| D | MCSubtargetInfo.h | 129 unsigned DefIdx) const { in getWriteLatencyEntry() argument
130 assert(DefIdx < SC->NumWriteLatencyEntries && in getWriteLatencyEntry()
133 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx]; in getWriteLatencyEntry()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCInstrItineraries.h | 181 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding() argument
185 if ((FirstDefIdx + DefIdx) >= LastDefIdx) in hasPipelineForwarding()
187 if (Forwardings[FirstDefIdx + DefIdx] == 0) in hasPipelineForwarding()
195 return Forwardings[FirstDefIdx + DefIdx] == in hasPipelineForwarding()
202 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency() argument
207 int DefCycle = getOperandCycle(DefClass, DefIdx); in getOperandLatency()
217 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
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| D | MCSubtargetInfo.h | 170 unsigned DefIdx) const { in getWriteLatencyEntry() argument
171 assert(DefIdx < SC->NumWriteLatencyEntries && in getWriteLatencyEntry()
174 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx]; in getWriteLatencyEntry()
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| /external/llvm-project/llvm/include/llvm/MC/ |
| D | MCInstrItineraries.h | 184 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding() argument
188 if ((FirstDefIdx + DefIdx) >= LastDefIdx) in hasPipelineForwarding()
190 if (Forwardings[FirstDefIdx + DefIdx] == 0) in hasPipelineForwarding()
198 return Forwardings[FirstDefIdx + DefIdx] == in hasPipelineForwarding()
205 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency() argument
210 int DefCycle = getOperandCycle(DefClass, DefIdx); in getOperandLatency()
220 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
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| /external/llvm/lib/CodeGen/ |
| D | TargetSchedule.cpp | 128 unsigned DefIdx = 0; in findDefIdx() local
132 ++DefIdx; in findDefIdx()
134 return DefIdx; in findDefIdx()
188 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
189 if (DefIdx < SCDesc->NumWriteLatencyEntries) { in computeOperandLatency()
192 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeOperandLatency()
214 errs() << "DefIdx " << DefIdx << " exceeds machine model writes for " in computeOperandLatency()
228 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
229 DefIdx != DefEnd; ++DefIdx) { in computeInstrLatency()
232 STI->getWriteLatencyEntry(&SCDesc, DefIdx); in computeInstrLatency()
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| D | PeepholeOptimizer.cpp | 296 unsigned DefIdx; member in __anoncaae1f320111::ValueTracker
354 : Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg), in ValueTracker()
358 DefIdx = MRI.def_begin(Reg).getOperandNo(); in ValueTracker()
369 ValueTracker(const MachineInstr &MI, unsigned DefIdx, unsigned DefSubReg, in ValueTracker() argument
373 : Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg), in ValueTracker()
375 assert(DefIdx < Def->getDesc().getNumDefs() && in ValueTracker()
376 Def->getOperand(DefIdx).isReg() && "Invalid definition"); in ValueTracker()
377 Reg = Def->getOperand(DefIdx).getReg(); in ValueTracker()
1672 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) in getNextSourceFromCopy()
1691 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) in getNextSourceFromBitcast()
[all …]
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| D | TargetInstrInfo.cpp | 982 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
992 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
994 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1056 unsigned DefIdx) const { in hasLowDefLatency()
1062 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
1070 unsigned DefIdx, in getOperandLatency() argument
1075 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1096 unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const { in computeOperandLatency() argument
1106 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, *UseMI, UseIdx); in computeOperandLatency()
1109 OperLatency = ItinData->getOperandCycle(DefClass, DefIdx); in computeOperandLatency()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 55 const MachineInstr &MI, unsigned DefIdx,
68 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
84 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
282 const MachineInstr &DefMI, unsigned DefIdx,
286 SDNode *DefNode, unsigned DefIdx,
309 unsigned DefIdx, unsigned DefAlign) const;
313 unsigned DefIdx, unsigned DefAlign) const;
324 unsigned DefIdx, unsigned DefAlign,
329 const MachineInstr &DefMI, unsigned DefIdx,
346 const MachineInstr &DefMI, unsigned DefIdx,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetSchedule.cpp | 158 unsigned DefIdx = 0; in findDefIdx() local
162 ++DefIdx; in findDefIdx()
164 return DefIdx; in findDefIdx()
218 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
219 if (DefIdx < SCDesc->NumWriteLatencyEntries) { in computeOperandLatency()
222 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeOperandLatency()
244 errs() << "DefIdx " << DefIdx << " exceeds machine model writes for " in computeOperandLatency()
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| D | TargetInstrInfo.cpp | 1037 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
1047 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
1049 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1111 unsigned DefIdx) const { in hasLowDefLatency()
1117 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
1189 unsigned DefIdx, in getOperandLatency() argument
1194 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1214 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceInputs() argument
1220 return getRegSequenceLikeInputs(MI, DefIdx, InputRegs); in getRegSequenceInputs()
1224 assert(DefIdx == 0 && "REG_SEQUENCE only has one def"); in getRegSequenceInputs()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetSchedule.cpp | 158 unsigned DefIdx = 0; in findDefIdx() local
162 ++DefIdx; in findDefIdx()
164 return DefIdx; in findDefIdx()
218 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
219 if (DefIdx < SCDesc->NumWriteLatencyEntries) { in computeOperandLatency()
222 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeOperandLatency()
244 errs() << "DefIdx " << DefIdx << " exceeds machine model writes for " in computeOperandLatency()
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| D | LiveIntervalCalc.cpp | 45 SlotIndex DefIdx = in createDeadDef() local
49 LR.createDeadDef(DefIdx, Alloc); in createDeadDef()
190 unsigned DefIdx; in extendToUses() local
193 else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) { in extendToUses()
196 isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber(); in extendToUses()
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| D | TargetInstrInfo.cpp | 1093 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
1103 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
1105 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1167 unsigned DefIdx) const { in hasLowDefLatency()
1173 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
1262 unsigned DefIdx, in getOperandLatency() argument
1267 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1287 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceInputs() argument
1293 return getRegSequenceLikeInputs(MI, DefIdx, InputRegs); in getRegSequenceInputs()
1297 assert(DefIdx == 0 && "REG_SEQUENCE only has one def"); in getRegSequenceInputs()
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| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | LegalizationArtifactCombiner.h | 511 unsigned DefIdx = 0; in getDefIndex() local
515 ++DefIdx; in getDefIndex()
518 return DefIdx; in getDefIndex()
615 for (unsigned j = 0, DefIdx = Idx * NewNumDefs; j < NewNumDefs; in tryCombineUnmergeValues() local
616 ++j, ++DefIdx) in tryCombineUnmergeValues()
617 DstRegs.push_back(MI.getOperand(DefIdx).getReg()); in tryCombineUnmergeValues()
668 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) { in tryCombineUnmergeValues() local
670 for (unsigned j = 0, Idx = NumRegs * DefIdx + 1; j < NumRegs; in tryCombineUnmergeValues()
674 Register DefReg = MI.getOperand(DefIdx).getReg(); in tryCombineUnmergeValues()
898 unsigned DefIdx = 0) {
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| /external/llvm-project/llvm/lib/MC/ |
| D | MCSchedule.cpp | 43 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
44 DefIdx != DefEnd; ++DefIdx) { in computeInstrLatency()
47 STI.getWriteLatencyEntry(&SCDesc, DefIdx); in computeInstrLatency()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/MC/ |
| D | MCSchedule.cpp | 43 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
44 DefIdx != DefEnd; ++DefIdx) { in computeInstrLatency()
47 STI.getWriteLatencyEntry(&SCDesc, DefIdx); in computeInstrLatency()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 59 const MachineInstr &MI, unsigned DefIdx,
72 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
88 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
318 const MachineInstr &DefMI, unsigned DefIdx,
322 SDNode *DefNode, unsigned DefIdx,
352 unsigned DefIdx, unsigned DefAlign) const;
356 unsigned DefIdx, unsigned DefAlign) const;
367 unsigned DefIdx, unsigned DefAlign,
372 const MachineInstr &DefMI, unsigned DefIdx,
389 const MachineInstr &DefMI, unsigned DefIdx,
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 391 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
409 getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
429 getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
934 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs() argument
948 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregLikeInputs() argument
962 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, in getInsertSubregLikeInputs() argument
1221 SDNode *DefNode, unsigned DefIdx,
1233 const MachineInstr &DefMI, unsigned DefIdx,
1249 const MachineInstr &DefMI, unsigned DefIdx,
1282 const MachineInstr &DefMI, unsigned DefIdx, in hasHighOperandLatency() argument
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 61 const MachineInstr &MI, unsigned DefIdx,
74 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
90 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
316 const MachineInstr &DefMI, unsigned DefIdx,
320 SDNode *DefNode, unsigned DefIdx,
404 unsigned DefIdx, unsigned DefAlign) const;
408 unsigned DefIdx, unsigned DefAlign) const;
419 unsigned DefIdx, unsigned DefAlign,
424 const MachineInstr &DefMI, unsigned DefIdx,
441 const MachineInstr &DefMI, unsigned DefIdx,
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 119 const MachineInstr &DefMI, unsigned DefIdx,
123 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
125 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, in getOperandLatency()
131 unsigned DefIdx) const override { in hasLowDefLatency() argument
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| D | PPCVSXSwapRemoval.cpp | 617 int DefIdx = SwapMap[DefMI]; in formWebs() local
618 (void)EC->unionSets(SwapVector[DefIdx].VSEId, in formWebs()
621 DEBUG(dbgs() << format("Unioning %d with %d\n", SwapVector[DefIdx].VSEId, in formWebs()
696 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs() local
698 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad || in recordUnoptimizableWebs()
699 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
705 DEBUG(dbgs() << " def " << DefIdx << ": "); in recordUnoptimizableWebs()
771 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval() local
772 SwapVector[DefIdx].WillRemove = 1; in markSwapsForRemoval()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXSwapRemoval.cpp | 620 int DefIdx = SwapMap[DefMI]; in formWebs() local
621 (void)EC->unionSets(SwapVector[DefIdx].VSEId, in formWebs()
625 SwapVector[DefIdx].VSEId, in formWebs()
701 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs() local
703 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad || in recordUnoptimizableWebs()
704 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
710 LLVM_DEBUG(dbgs() << " def " << DefIdx << ": "); in recordUnoptimizableWebs()
777 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval() local
778 SwapVector[DefIdx].WillRemove = 1; in markSwapsForRemoval()
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCVSXSwapRemoval.cpp | 620 int DefIdx = SwapMap[DefMI]; in formWebs() local
621 (void)EC->unionSets(SwapVector[DefIdx].VSEId, in formWebs()
625 SwapVector[DefIdx].VSEId, in formWebs()
724 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs() local
726 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad || in recordUnoptimizableWebs()
727 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
733 LLVM_DEBUG(dbgs() << " def " << DefIdx << ": "); in recordUnoptimizableWebs()
800 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval() local
801 SwapVector[DefIdx].WillRemove = 1; in markSwapsForRemoval()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | LegalizationArtifactCombiner.h | 327 for (unsigned j = 0, DefIdx = Idx * NewNumDefs; j < NewNumDefs; in tryCombineMerges() local
328 ++j, ++DefIdx) in tryCombineMerges()
329 DstRegs.push_back(MI.getOperand(DefIdx).getReg()); in tryCombineMerges()
363 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) { in tryCombineMerges() local
365 for (unsigned j = 0, Idx = NumRegs * DefIdx + 1; j < NumRegs; in tryCombineMerges()
369 Register DefReg = MI.getOperand(DefIdx).getReg(); in tryCombineMerges()
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