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Searched refs:DefReg (Results 1 – 25 of 72) sorted by relevance

123

/external/llvm/lib/Target/AArch64/
DAArch64RedundantCopyElimination.cpp126 unsigned DefReg = MI->getOperand(0).getReg(); in optimizeCopy() local
130 !MRI->isReserved(DefReg) && in optimizeCopy()
131 (TargetReg == DefReg || TRI->isSuperRegister(DefReg, TargetReg))) { in optimizeCopy()
140 TRI->isSubRegister(SmallestDef, DefReg) ? DefReg : SmallestDef; in optimizeCopy()
/external/llvm/lib/CodeGen/
DDetectDeadLanes.cpp256 unsigned DefReg = Def.getReg(); in transferUsedLanes() local
257 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in transferUsedLanes()
291 unsigned DefReg = Def.getReg(); in transferDefinedLanesStep() local
292 if (!TargetRegisterInfo::isVirtualRegister(DefReg)) in transferDefinedLanesStep()
294 unsigned DefRegIdx = TargetRegisterInfo::virtReg2Index(DefReg); in transferDefinedLanesStep()
434 unsigned DefReg = Def.getReg(); in determineInitialUsedLanes() local
437 if (TargetRegisterInfo::isVirtualRegister(DefReg)) { in determineInitialUsedLanes()
441 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes()
476 unsigned DefReg = Def.getReg(); in isUndefInput() local
477 if (!TargetRegisterInfo::isVirtualRegister(DefReg)) in isUndefInput()
[all …]
DImplicitNullChecks.cpp495 unsigned DefReg = NoRegister; in insertFaultingLoad() local
497 DefReg = LoadMI->defs().begin()->getReg(); in insertFaultingLoad()
502 auto MIB = BuildMI(MBB, DL, TII->get(TargetOpcode::FAULTING_LOAD_OP), DefReg) in insertFaultingLoad()
DTailDuplicator.cpp308 unsigned DefReg = MI->getOperand(0).getReg(); in processPHI() local
313 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in processPHI()
314 LocalVRMap.insert(std::make_pair(DefReg, RegSubRegPair(SrcReg, SrcSubReg))); in processPHI()
320 if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg)) in processPHI()
321 addSSAUpdateEntry(DefReg, NewDef, PredBB); in processPHI()
/external/llvm-project/llvm/lib/CodeGen/
DDetectDeadLanes.cpp250 Register DefReg = Def.getReg(); in transferUsedLanes() local
251 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in transferUsedLanes()
285 Register DefReg = Def.getReg(); in transferDefinedLanesStep() local
286 if (!Register::isVirtualRegister(DefReg)) in transferDefinedLanesStep()
288 unsigned DefRegIdx = Register::virtReg2Index(DefReg); in transferDefinedLanesStep()
428 Register DefReg = Def.getReg(); in determineInitialUsedLanes() local
431 if (Register::isVirtualRegister(DefReg)) { in determineInitialUsedLanes()
435 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes()
470 Register DefReg = Def.getReg(); in isUndefInput() local
471 if (!Register::isVirtualRegister(DefReg)) in isUndefInput()
[all …]
DTailDuplicator.cpp352 Register DefReg = MI->getOperand(0).getReg(); in processPHI() local
357 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in processPHI()
358 LocalVRMap.insert(std::make_pair(DefReg, RegSubRegPair(SrcReg, SrcSubReg))); in processPHI()
364 if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg)) in processPHI()
365 addSSAUpdateEntry(DefReg, NewDef, PredBB); in processPHI()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DDetectDeadLanes.cpp253 Register DefReg = Def.getReg(); in transferUsedLanes() local
254 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in transferUsedLanes()
288 Register DefReg = Def.getReg(); in transferDefinedLanesStep() local
289 if (!Register::isVirtualRegister(DefReg)) in transferDefinedLanesStep()
291 unsigned DefRegIdx = Register::virtReg2Index(DefReg); in transferDefinedLanesStep()
431 Register DefReg = Def.getReg(); in determineInitialUsedLanes() local
434 if (Register::isVirtualRegister(DefReg)) { in determineInitialUsedLanes()
438 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes()
473 Register DefReg = Def.getReg(); in isUndefInput() local
474 if (!Register::isVirtualRegister(DefReg)) in isUndefInput()
[all …]
DTailDuplicator.cpp350 Register DefReg = MI->getOperand(0).getReg(); in processPHI() local
355 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in processPHI()
356 LocalVRMap.insert(std::make_pair(DefReg, RegSubRegPair(SrcReg, SrcSubReg))); in processPHI()
362 if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg)) in processPHI()
363 addSSAUpdateEntry(DefReg, NewDef, PredBB); in processPHI()
/external/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyRegStackify.cpp475 Register DefReg = MO.getReg(); in oneUseDominatesOtherUses() local
476 if (!Register::isVirtualRegister(DefReg) || in oneUseDominatesOtherUses()
477 !MFI.isVRegStackified(DefReg)) in oneUseDominatesOtherUses()
479 assert(MRI.hasOneNonDBGUse(DefReg)); in oneUseDominatesOtherUses()
480 const MachineOperand &NewUse = *MRI.use_nodbg_begin(DefReg); in oneUseDominatesOtherUses()
647 Register DefReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse() local
652 .addReg(DefReg, getUndefRegState(DefMO.isDead())); in moveAndTeeForMultiUse()
654 DefMO.setReg(DefReg); in moveAndTeeForMultiUse()
670 LIS.createAndComputeVirtRegInterval(DefReg); in moveAndTeeForMultiUse()
671 MFI.stackifyVReg(MRI, DefReg); in moveAndTeeForMultiUse()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyRegStackify.cpp439 Register DefReg = MO.getReg(); in oneUseDominatesOtherUses() local
440 if (!Register::isVirtualRegister(DefReg) || in oneUseDominatesOtherUses()
441 !MFI.isVRegStackified(DefReg)) in oneUseDominatesOtherUses()
443 assert(MRI.hasOneNonDBGUse(DefReg)); in oneUseDominatesOtherUses()
444 const MachineOperand &NewUse = *MRI.use_nodbg_begin(DefReg); in oneUseDominatesOtherUses()
611 Register DefReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse() local
616 .addReg(DefReg, getUndefRegState(DefMO.isDead())); in moveAndTeeForMultiUse()
618 DefMO.setReg(DefReg); in moveAndTeeForMultiUse()
634 LIS.createAndComputeVirtRegInterval(DefReg); in moveAndTeeForMultiUse()
635 MFI.stackifyVReg(DefReg); in moveAndTeeForMultiUse()
[all …]
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyRegStackify.cpp392 unsigned DefReg = MO.getReg(); in OneUseDominatesOtherUses() local
393 if (!TargetRegisterInfo::isVirtualRegister(DefReg) || in OneUseDominatesOtherUses()
394 !MFI.isVRegStackified(DefReg)) in OneUseDominatesOtherUses()
396 assert(MRI.hasOneUse(DefReg)); in OneUseDominatesOtherUses()
397 const MachineOperand &NewUse = *MRI.use_begin(DefReg); in OneUseDominatesOtherUses()
549 unsigned DefReg = MRI.createVirtualRegister(RegClass); in MoveAndTeeForMultiUse() local
554 .addReg(DefReg, getUndefRegState(DefMO.isDead())); in MoveAndTeeForMultiUse()
556 DefMO.setReg(DefReg); in MoveAndTeeForMultiUse()
570 LIS.createAndComputeVirtRegInterval(DefReg); in MoveAndTeeForMultiUse()
571 MFI.stackifyVReg(DefReg); in MoveAndTeeForMultiUse()
/external/llvm-project/llvm/lib/Target/X86/
DX86InstructionSelector.cpp508 const Register DefReg = I.getOperand(0).getReg(); in selectLoadStoreOp() local
509 LLT Ty = MRI.getType(DefReg); in selectLoadStoreOp()
510 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp()
546 addFullAddress(MIB, AM).addUse(DefReg); in selectLoadStoreOp()
568 const Register DefReg = I.getOperand(0).getReg(); in selectFrameIndexOrGep() local
569 LLT Ty = MRI.getType(DefReg); in selectFrameIndexOrGep()
621 const Register DefReg = I.getOperand(0).getReg(); in selectGlobalValue() local
622 LLT Ty = MRI.getType(DefReg); in selectGlobalValue()
640 const Register DefReg = I.getOperand(0).getReg(); in selectConstant() local
641 LLT Ty = MRI.getType(DefReg); in selectConstant()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstructionSelector.cpp507 const Register DefReg = I.getOperand(0).getReg(); in selectLoadStoreOp() local
508 LLT Ty = MRI.getType(DefReg); in selectLoadStoreOp()
509 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp()
545 addFullAddress(MIB, AM).addUse(DefReg); in selectLoadStoreOp()
567 const Register DefReg = I.getOperand(0).getReg(); in selectFrameIndexOrGep() local
568 LLT Ty = MRI.getType(DefReg); in selectFrameIndexOrGep()
620 const Register DefReg = I.getOperand(0).getReg(); in selectGlobalValue() local
621 LLT Ty = MRI.getType(DefReg); in selectGlobalValue()
639 const Register DefReg = I.getOperand(0).getReg(); in selectConstant() local
640 LLT Ty = MRI.getType(DefReg); in selectConstant()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64RedundantCopyElimination.cpp382 Register DefReg = MI->getOperand(0).getReg(); in optimizeBlock() local
385 if (!MRI->isReserved(DefReg) && in optimizeBlock()
389 if (KnownReg.Reg != DefReg && in optimizeBlock()
390 !TRI->isSuperRegister(DefReg, KnownReg.Reg)) in optimizeBlock()
DAArch64InstructionSelector.cpp145 MachineInstr *emitADD(Register DefReg, MachineOperand &LHS, MachineOperand &RHS,
163 MachineInstr *emitCSetForICMP(Register DefReg, unsigned Pred,
1392 Register DefReg = I.getOperand(0).getReg(); in earlySelect() local
1393 LLT Ty = MRI.getType(DefReg); in earlySelect()
1399 RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI); in earlySelect()
1402 RBI.constrainGenericRegister(DefReg, AArch64::GPR32RegClass, MRI); in earlySelect()
1429 const Register DefReg = I.getOperand(0).getReg(); in select() local
1430 const LLT DefTy = MRI.getType(DefReg); in select()
1433 MRI.getRegClassOrRegBank(DefReg); in select()
1452 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI); in select()
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64RedundantCopyElimination.cpp382 Register DefReg = MI->getOperand(0).getReg(); in optimizeBlock() local
385 if (!MRI->isReserved(DefReg) && in optimizeBlock()
389 if (KnownReg.Reg != DefReg && in optimizeBlock()
390 !TRI->isSuperRegister(DefReg, KnownReg.Reg)) in optimizeBlock()
/external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
DLegalizationArtifactCombiner.h383 Register DefReg = MI.getOperand(I).getReg(); in tryFoldUnmergeCast() local
384 UpdatedDefs.push_back(DefReg); in tryFoldUnmergeCast()
385 Builder.buildTrunc(DefReg, NewUnmerge.getReg(I)); in tryFoldUnmergeCast()
674 Register DefReg = MI.getOperand(DefIdx).getReg(); in tryCombineUnmergeValues() local
675 Builder.buildMerge(DefReg, Regs); in tryCombineUnmergeValues()
676 UpdatedDefs.push_back(DefReg); in tryCombineUnmergeValues()
690 Register DefReg = MI.getOperand(Idx).getReg(); in tryCombineUnmergeValues() local
691 Builder.buildInstr(ConvertOp, {DefReg}, {MergeSrc}); in tryCombineUnmergeValues()
692 UpdatedDefs.push_back(DefReg); in tryCombineUnmergeValues()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DLegalizationArtifactCombiner.h369 Register DefReg = MI.getOperand(DefIdx).getReg(); in tryCombineMerges() local
370 Builder.buildMerge(DefReg, Regs); in tryCombineMerges()
371 UpdatedDefs.push_back(DefReg); in tryCombineMerges()
385 Register DefReg = MI.getOperand(Idx).getReg(); in tryCombineMerges() local
386 Builder.buildInstr(ConvertOp, {DefReg}, {MergeSrc}); in tryCombineMerges()
387 UpdatedDefs.push_back(DefReg); in tryCombineMerges()
/external/llvm/lib/Target/PowerPC/
DPPCVSXSwapRemoval.cpp665 unsigned DefReg = MI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
671 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
695 unsigned DefReg = DefMI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
714 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
753 unsigned DefReg = MI->getOperand(0).getReg(); in markSwapsForRemoval() local
755 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in markSwapsForRemoval()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCVSXSwapRemoval.cpp670 Register DefReg = MI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
676 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
700 Register DefReg = DefMI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
719 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
759 Register DefReg = MI->getOperand(0).getReg(); in markSwapsForRemoval() local
761 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in markSwapsForRemoval()
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCVSXSwapRemoval.cpp670 Register DefReg = MI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
676 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
723 Register DefReg = DefMI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
742 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
782 Register DefReg = MI->getOperand(0).getReg(); in markSwapsForRemoval() local
784 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in markSwapsForRemoval()
DPPCPreEmitPeephole.cpp255 Register DefReg; in addLinkerOpt() member
287 if (!BBI->readsRegister(Pair.DefReg, TRI) && in addLinkerOpt()
288 !BBI->modifiesRegister(Pair.DefReg, TRI)) in addLinkerOpt()
297 if (UseOp && UseOp->isReg() && UseOp->getReg() == Pair.DefReg && in addLinkerOpt()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips16InstrInfo.cpp369 int DefReg = 0; in loadImmediate() local
373 DefReg = MO.getReg(); in loadImmediate()
392 if (DefReg != Reg) { in loadImmediate()
407 if (DefReg!= SpReg) { in loadImmediate()
/external/llvm-project/llvm/lib/Target/Mips/
DMips16InstrInfo.cpp369 int DefReg = 0; in loadImmediate() local
373 DefReg = MO.getReg(); in loadImmediate()
392 if (DefReg != Reg) { in loadImmediate()
407 if (DefReg!= SpReg) { in loadImmediate()
/external/llvm/lib/Target/Mips/
DMips16InstrInfo.cpp354 int DefReg = 0; in loadImmediate() local
358 DefReg = MO.getReg(); in loadImmediate()
377 if (DefReg != Reg) { in loadImmediate()
392 if (DefReg!= SpReg) { in loadImmediate()

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