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Searched refs:DestRC (Results 1 – 15 of 15) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.cpp37 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg); in copyPhysReg() local
40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
44 if (DestRC == &NVPTX::Int1RegsRegClass) { in copyPhysReg()
46 } else if (DestRC == &NVPTX::Int16RegsRegClass) { in copyPhysReg()
48 } else if (DestRC == &NVPTX::Int32RegsRegClass) { in copyPhysReg()
51 } else if (DestRC == &NVPTX::Int64RegsRegClass) { in copyPhysReg()
54 } else if (DestRC == &NVPTX::Float16RegsRegClass) { in copyPhysReg()
57 } else if (DestRC == &NVPTX::Float16x2RegsRegClass) { in copyPhysReg()
59 } else if (DestRC == &NVPTX::Float32RegsRegClass) { in copyPhysReg()
62 } else if (DestRC == &NVPTX::Float64RegsRegClass) { in copyPhysReg()
/external/llvm-project/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.cpp37 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg); in copyPhysReg() local
40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
44 if (DestRC == &NVPTX::Int1RegsRegClass) { in copyPhysReg()
46 } else if (DestRC == &NVPTX::Int16RegsRegClass) { in copyPhysReg()
48 } else if (DestRC == &NVPTX::Int32RegsRegClass) { in copyPhysReg()
51 } else if (DestRC == &NVPTX::Int64RegsRegClass) { in copyPhysReg()
54 } else if (DestRC == &NVPTX::Float16RegsRegClass) { in copyPhysReg()
57 } else if (DestRC == &NVPTX::Float16x2RegsRegClass) { in copyPhysReg()
59 } else if (DestRC == &NVPTX::Float32RegsRegClass) { in copyPhysReg()
62 } else if (DestRC == &NVPTX::Float64RegsRegClass) { in copyPhysReg()
/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.cpp38 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg); in copyPhysReg() local
41 if (DestRC->getSize() != SrcRC->getSize()) in copyPhysReg()
45 if (DestRC == &NVPTX::Int1RegsRegClass) { in copyPhysReg()
47 } else if (DestRC == &NVPTX::Int16RegsRegClass) { in copyPhysReg()
49 } else if (DestRC == &NVPTX::Int32RegsRegClass) { in copyPhysReg()
52 } else if (DestRC == &NVPTX::Int64RegsRegClass) { in copyPhysReg()
55 } else if (DestRC == &NVPTX::Float32RegsRegClass) { in copyPhysReg()
58 } else if (DestRC == &NVPTX::Float64RegsRegClass) { in copyPhysReg()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGFast.cpp381 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
386 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
389 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
575 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in ListScheduleBottomUp() local
585 if (DestRC != RC) { in ListScheduleBottomUp()
587 if (!DestRC && !NewDef) in ListScheduleBottomUp()
594 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in ListScheduleBottomUp()
DScheduleDAGRRList.cpp1223 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
1228 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
1231 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
1559 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in PickNodeToScheduleBottomUp() local
1569 if (DestRC != RC) { in PickNodeToScheduleBottomUp()
1571 if (!DestRC && !NewDef) in PickNodeToScheduleBottomUp()
1577 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in PickNodeToScheduleBottomUp()
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGFast.cpp388 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
393 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
396 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
583 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in ListScheduleBottomUp() local
593 if (DestRC != RC) { in ListScheduleBottomUp()
595 if (!DestRC && !NewDef) in ListScheduleBottomUp()
602 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in ListScheduleBottomUp()
DScheduleDAGRRList.cpp1136 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
1141 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
1144 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
1449 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in PickNodeToScheduleBottomUp() local
1459 if (DestRC != RC) { in PickNodeToScheduleBottomUp()
1461 if (!DestRC && !NewDef) in PickNodeToScheduleBottomUp()
1467 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in PickNodeToScheduleBottomUp()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGFast.cpp381 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
386 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
389 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
575 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in ListScheduleBottomUp() local
585 if (DestRC != RC) { in ListScheduleBottomUp()
587 if (!DestRC && !NewDef) in ListScheduleBottomUp()
594 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in ListScheduleBottomUp()
DScheduleDAGRRList.cpp1223 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
1228 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
1231 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
1559 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in PickNodeToScheduleBottomUp() local
1569 if (DestRC != RC) { in PickNodeToScheduleBottomUp()
1571 if (!DestRC && !NewDef) in PickNodeToScheduleBottomUp()
1577 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in PickNodeToScheduleBottomUp()
/external/llvm/lib/Target/AMDGPU/
DSIFoldOperands.cpp238 const TargetRegisterClass *DestRC in foldOperand() local
243 unsigned MovOp = TII->getMovOpcode(DestRC); in foldOperand()
DSIInstrInfo.cpp2718 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitUnaryOp() local
2719 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitUnaryOp()
2779 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitBinaryOp() local
2780 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitBinaryOp()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIFoldOperands.cpp643 const TargetRegisterClass *DestRC = MRI->getRegClass(DestReg); in foldOperand() local
648 if (TRI->isSGPRClass(SrcRC) && TRI->hasVectorRegisters(DestRC)) { in foldOperand()
666 if (DestRC == &AMDGPU::AGPR_32RegClass && in foldOperand()
677 unsigned MovOp = TII->getMovOpcode(DestRC); in foldOperand()
DSIInstrInfo.cpp5317 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitUnaryOp() local
5318 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitUnaryOp()
5455 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitBinaryOp() local
5456 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitBinaryOp()
5498 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitXnor() local
5516 Register NewDest = MRI.createVirtualRegister(DestRC); in splitScalar64BitXnor()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIFoldOperands.cpp672 const TargetRegisterClass *DestRC = TRI->getRegClassForReg(*MRI, DestReg); in foldOperand() local
674 if (TRI->isSGPRClass(SrcRC) && TRI->hasVectorRegisters(DestRC)) { in foldOperand()
694 if (DestRC == &AMDGPU::AGPR_32RegClass && in foldOperand()
706 unsigned MovOp = TII->getMovOpcode(DestRC); in foldOperand()
DSIInstrInfo.cpp6049 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitUnaryOp() local
6050 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitUnaryOp()
6187 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitBinaryOp() local
6188 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitBinaryOp()
6230 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitXnor() local
6248 Register NewDest = MRI.createVirtualRegister(DestRC); in splitScalar64BitXnor()