Searched refs:DivScale1 (Results 1 – 5 of 5) sorted by relevance
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | AMDGPULegalizerInfo.cpp | 2160 auto DivScale1 = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S64, S1}, false) in legalizeFDIV64() local 2167 auto Mul = B.buildMul(S64, DivScale1.getReg(0), Fma3, Flags); in legalizeFDIV64() 2168 auto Fma4 = B.buildFMA(S64, NegDivScale0, Mul, DivScale1.getReg(0), Flags); in legalizeFDIV64() 2182 auto Scale1Unmerge = B.buildUnmerge(S32, DivScale1); in legalizeFDIV64() 2190 Scale = DivScale1.getReg(1); in legalizeFDIV64()
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D | SIISelLowering.cpp | 7831 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X); in LowerFDIV64() local 7834 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3); in LowerFDIV64() 7837 NegDivScale0, Mul, DivScale1); in LowerFDIV64() 7851 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1); in LowerFDIV64() 7865 Scale = DivScale1.getValue(1); in LowerFDIV64()
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/external/llvm/lib/Target/AMDGPU/ |
D | SIISelLowering.cpp | 2249 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X); in LowerFDIV64() local 2252 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3); in LowerFDIV64() 2255 NegDivScale0, Mul, DivScale1); in LowerFDIV64() 2269 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1); in LowerFDIV64() 2283 Scale = DivScale1.getValue(1); in LowerFDIV64()
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/external/llvm-project/llvm/lib/Target/AMDGPU/ |
D | AMDGPULegalizerInfo.cpp | 3267 auto DivScale1 = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S64, S1}, false) in legalizeFDIV64() local 3274 auto Mul = B.buildFMul(S64, DivScale1.getReg(0), Fma3, Flags); in legalizeFDIV64() 3275 auto Fma4 = B.buildFMA(S64, NegDivScale0, Mul, DivScale1.getReg(0), Flags); in legalizeFDIV64() 3287 auto Scale1Unmerge = B.buildUnmerge(S32, DivScale1); in legalizeFDIV64() 3295 Scale = DivScale1.getReg(1); in legalizeFDIV64()
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D | SIISelLowering.cpp | 8509 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X); in LowerFDIV64() local 8512 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3); in LowerFDIV64() 8515 NegDivScale0, Mul, DivScale1); in LowerFDIV64() 8529 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1); in LowerFDIV64() 8543 Scale = DivScale1.getValue(1); in LowerFDIV64()
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