| /external/llvm-project/clang/lib/CodeGen/ |
| D | CGNonTrivialStruct.cpp | 33 enum { DstIdx = 0, SrcIdx = 1 }; enumerator
362 Address DstAddr = StartAddrs[DstIdx]; in visitArray()
393 CGF.Builder.CreateICmpEQ(PHIs[DstIdx], DstArrayEnd, "done"); in visitArray()
526 Address DstAddr = this->getAddrWithOffset(Addrs[DstIdx], this->Start); in flushTrivialFields()
562 Address DstAddr = this->getAddrWithOffset(Addrs[DstIdx], Offset); in visitVolatileTrivial()
572 Address DstAddr = this->CGF->Builder.CreateBitCast(Addrs[DstIdx], Ty); in visitVolatileTrivial()
603 *CGF, getAddrWithOffset(Addrs[DstIdx], CurStructOffset, FD), QT); in visitARCStrong()
609 *CGF, getAddrWithOffset(Addrs[DstIdx], CurStructOffset, FD), QT); in visitARCWeak()
615 CGF->MakeAddrLValue(getAddrWithOffset(Addrs[DstIdx], Offset), FT)); in callSpecialFunction()
644 getAddrWithOffset(Addrs[DstIdx], CurStructOffset, FD), QT); in visitARCStrong()
[all …]
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| /external/llvm/lib/CodeGen/ |
| D | RegisterCoalescer.h | 39 unsigned DstIdx; variable
61 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0), in CoalescerPair()
68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0), in CoalescerPair()
106 unsigned getDstIdx() const { return DstIdx; } in getDstIdx()
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| D | RegisterCoalescer.cpp | 315 SrcIdx = DstIdx = 0; in setRegisters()
362 SrcIdx, DstIdx); in setRegisters()
371 DstIdx = SrcSub; in setRegisters()
384 if (DstIdx && !SrcIdx) { in setRegisters()
386 std::swap(SrcIdx, DstIdx); in setRegisters()
405 std::swap(SrcIdx, DstIdx); in flip()
429 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state."); in isCoalescable()
444 TRI.composeSubRegIndices(DstIdx, DstSub); in isCoalescable()
887 unsigned DstIdx = CP.isFlipped() ? CP.getSrcIdx() : CP.getDstIdx(); in reMaterializeTrivialDef() local
927 if (SrcIdx && DstIdx) in reMaterializeTrivialDef()
[all …]
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| D | TwoAddressInstructionPass.cpp | 132 unsigned SrcIdx, unsigned DstIdx,
1211 unsigned SrcIdx, unsigned DstIdx, in tryInstructionTransform() argument
1217 unsigned regA = MI.getOperand(DstIdx).getReg(); in tryInstructionTransform()
1227 bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist); in tryInstructionTransform()
1409 unsigned DstIdx = 0; in collectTiedOperands() local
1410 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx)) in collectTiedOperands()
1414 MachineOperand &DstMO = MI->getOperand(DstIdx); in collectTiedOperands()
1435 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx)); in collectTiedOperands()
1460 unsigned DstIdx = TiedPairs[tpi].second; in processTiedPairs() local
1462 const MachineOperand &DstMO = MI->getOperand(DstIdx); in processTiedPairs()
[all …]
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIAddIMGInit.cpp | 97 int DstIdx = in runOnMachineFunction() local
122 RI->getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32; in runOnMachineFunction()
128 MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in runOnMachineFunction()
146 MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in runOnMachineFunction()
166 MI.tieOperands(DstIdx, MI.getNumOperands() - 1); in runOnMachineFunction()
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| D | R600ExpandSpecialInstrs.cpp | 98 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in runOnMachineFunction() local
99 assert(DstIdx != -1); in runOnMachineFunction()
100 MachineOperand &DstOp = MI.getOperand(DstIdx); in runOnMachineFunction()
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| D | R600Packetizer.cpp | 89 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst); in getPreviousVector() local
90 if (DstIdx == -1) { in getPreviousVector()
93 Register Dst = BI->getOperand(DstIdx).getReg(); in getPreviousVector()
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| D | SIPeepholeSDWA.cpp | 403 auto DstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), in convertToSDWA() local
405 auto TiedIdx = MI.findTiedOperandIdx(DstIdx); in convertToSDWA()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIAddIMGInit.cpp | 98 int DstIdx = in runOnMachineFunction() local
127 RI->getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32; in runOnMachineFunction()
133 MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in runOnMachineFunction()
151 MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in runOnMachineFunction()
171 MI.tieOperands(DstIdx, MI.getNumOperands() - 1); in runOnMachineFunction()
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| D | R600ExpandSpecialInstrs.cpp | 98 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in runOnMachineFunction() local
99 assert(DstIdx != -1); in runOnMachineFunction()
100 MachineOperand &DstOp = MI.getOperand(DstIdx); in runOnMachineFunction()
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| D | R600Packetizer.cpp | 89 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst); in getPreviousVector() local
90 if (DstIdx == -1) { in getPreviousVector()
93 Register Dst = BI->getOperand(DstIdx).getReg(); in getPreviousVector()
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| D | SIPeepholeSDWA.cpp | 403 auto DstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), in convertToSDWA() local
405 auto TiedIdx = MI.findTiedOperandIdx(DstIdx); in convertToSDWA()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | RegisterCoalescer.h | 37 unsigned DstIdx = 0; variable
101 unsigned getDstIdx() const { return DstIdx; } in getDstIdx()
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| D | TwoAddressInstructionPass.cpp | 136 bool commuteInstruction(MachineInstr *MI, unsigned DstIdx,
156 unsigned SrcIdx, unsigned DstIdx,
681 unsigned DstIdx, in commuteInstruction() argument
702 Register RegA = MI->getOperand(DstIdx).getReg(); in commuteInstruction()
1271 unsigned SrcIdx, unsigned DstIdx, in tryInstructionTransform() argument
1277 Register regA = MI.getOperand(DstIdx).getReg(); in tryInstructionTransform()
1287 bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist); in tryInstructionTransform()
1468 unsigned DstIdx = 0; in collectTiedOperands() local
1469 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx)) in collectTiedOperands()
1473 MachineOperand &DstMO = MI->getOperand(DstIdx); in collectTiedOperands()
[all …]
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| D | RegisterCoalescer.cpp | 244 unsigned DstIdx);
428 SrcIdx = DstIdx = 0; in setRegisters()
475 SrcIdx, DstIdx); in setRegisters()
484 DstIdx = SrcSub; in setRegisters()
497 if (DstIdx && !SrcIdx) { in setRegisters()
499 std::swap(SrcIdx, DstIdx); in setRegisters()
518 std::swap(SrcIdx, DstIdx); in flip()
542 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state."); in isCoalescable()
557 TRI.composeSubRegIndices(DstIdx, DstSub); in isCoalescable()
1240 unsigned DstIdx = CP.isFlipped() ? CP.getSrcIdx() : CP.getDstIdx(); in reMaterializeTrivialDef() local
[all …]
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | RegisterCoalescer.h | 39 unsigned DstIdx = 0; variable
103 unsigned getDstIdx() const { return DstIdx; } in getDstIdx()
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| D | TwoAddressInstructionPass.cpp | 128 bool commuteInstruction(MachineInstr *MI, unsigned DstIdx,
146 unsigned SrcIdx, unsigned DstIdx,
538 unsigned DstIdx, in commuteInstruction() argument
559 Register RegA = MI->getOperand(DstIdx).getReg(); in commuteInstruction()
1127 unsigned SrcIdx, unsigned DstIdx, in tryInstructionTransform() argument
1133 Register regA = MI.getOperand(DstIdx).getReg(); in tryInstructionTransform()
1142 bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist); in tryInstructionTransform()
1323 unsigned DstIdx = 0; in collectTiedOperands() local
1324 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx)) in collectTiedOperands()
1328 MachineOperand &DstMO = MI->getOperand(DstIdx); in collectTiedOperands()
[all …]
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| D | RegisterCoalescer.cpp | 244 unsigned DstIdx);
428 SrcIdx = DstIdx = 0; in setRegisters()
476 SrcIdx, DstIdx); in setRegisters()
485 DstIdx = SrcSub; in setRegisters()
498 if (DstIdx && !SrcIdx) { in setRegisters()
500 std::swap(SrcIdx, DstIdx); in setRegisters()
519 std::swap(SrcIdx, DstIdx); in flip()
544 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state."); in isCoalescable()
559 TRI.composeSubRegIndices(DstIdx, DstSub); in isCoalescable()
1254 unsigned DstIdx = CP.isFlipped() ? CP.getSrcIdx() : CP.getDstIdx(); in reMaterializeTrivialDef() local
[all …]
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| /external/llvm-project/llvm/test/CodeGen/PowerPC/ |
| D | mma-acc-memops.ll | 12 define void @testLdSt(i64 %SrcIdx, i64 %DstIdx) {
46 define void @testXLdSt(i64 %SrcIdx, i64 %DstIdx) {
84 %arrayidx1 = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 %DstIdx
134 define void @testLdStPair(i64 %SrcIdx, i64 %DstIdx) {
160 define void @testXLdStPair(i64 %SrcIdx, i64 %DstIdx) {
190 %arrayidx1 = getelementptr inbounds <256 x i1>, <256 x i1>* @g, i64 %DstIdx
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | GISelKnownBits.cpp | 438 unsigned DstIdx = 0; in computeKnownBitsImpl() local
439 for (; DstIdx != NumOps - 1 && MI.getOperand(DstIdx).getReg() != R; in computeKnownBitsImpl()
440 ++DstIdx) in computeKnownBitsImpl()
443 Known = SrcOpKnown.extractBits(BitWidth, BitWidth * DstIdx); in computeKnownBitsImpl()
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| D | LegalizerHelper.cpp | 4392 unsigned DstIdx = 0; // Low bits of the result. in multiplyRegisters() local
4394 B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0); in multiplyRegisters()
4395 DstRegs[DstIdx] = FactorSum; in multiplyRegisters()
4400 for (DstIdx = 1; DstIdx < DstParts; DstIdx++) { in multiplyRegisters()
4402 for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1; in multiplyRegisters()
4403 i <= std::min(DstIdx, SrcParts - 1); ++i) { in multiplyRegisters()
4405 B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]); in multiplyRegisters()
4409 for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts; in multiplyRegisters()
4410 i <= std::min(DstIdx - 1, SrcParts - 1); ++i) { in multiplyRegisters()
4412 B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]); in multiplyRegisters()
[all …]
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ExpandSpecialInstrs.cpp | 83 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst); in runOnMachineFunction() local
84 assert(DstIdx != -1); in runOnMachineFunction()
85 MachineOperand &DstOp = MI.getOperand(DstIdx); in runOnMachineFunction()
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| D | R600Packetizer.cpp | 92 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst); in getPreviousVector() local
93 if (DstIdx == -1) { in getPreviousVector()
96 unsigned Dst = BI->getOperand(DstIdx).getReg(); in getPreviousVector()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 3406 unsigned DstIdx = 0; // Low bits of the result. in multiplyRegisters() local
3408 B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0); in multiplyRegisters()
3409 DstRegs[DstIdx] = FactorSum; in multiplyRegisters()
3414 for (DstIdx = 1; DstIdx < DstParts; DstIdx++) { in multiplyRegisters()
3416 for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1; in multiplyRegisters()
3417 i <= std::min(DstIdx, SrcParts - 1); ++i) { in multiplyRegisters()
3419 B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]); in multiplyRegisters()
3423 for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts; in multiplyRegisters()
3424 i <= std::min(DstIdx - 1, SrcParts - 1); ++i) { in multiplyRegisters()
3426 B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]); in multiplyRegisters()
[all …]
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| /external/llvm/lib/Analysis/ |
| D | DependenceAnalysis.cpp | 3353 DstIdx = DstGEP->idx_begin(); in depends() local
3355 ++SrcIdx, ++DstIdx, ++P) { in depends()
3357 Pair[P].Dst = SE->getSCEV(*DstIdx); in depends()
3783 DstIdx = DstGEP->idx_begin(); in getSplitIteration() local
3785 ++SrcIdx, ++DstIdx, ++P) { in getSplitIteration()
3787 Pair[P].Dst = SE->getSCEV(*DstIdx); in getSplitIteration()
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