| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 58 class DstOp {
67 DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {} in DstOp() function
68 DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {} in DstOp() function
69 DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {} in DstOp() function
70 DstOp(const LLT T) : LLTTy(T), Ty(DstType::Ty_LLT) {} in DstOp() function
71 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {} in DstOp() function
420 MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size,
432 MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx);
444 MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV);
458 MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0,
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| D | CSEMIRBuilder.h | 56 void profileDstOp(const DstOp &Op, GISelInstProfileBuilder &B) const;
58 void profileDstOps(ArrayRef<DstOp> Ops, GISelInstProfileBuilder &B) const { in profileDstOps()
59 for (const DstOp &Op : Ops) in profileDstOps()
72 void profileEverything(unsigned Opc, ArrayRef<DstOp> DstOps,
82 MachineInstrBuilder generateCopiesIfRequired(ArrayRef<DstOp> DstOps,
88 bool checkCopyToDefsPossible(ArrayRef<DstOp> DstOps);
94 MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
100 MachineInstrBuilder buildConstant(const DstOp &Res,
105 MachineInstrBuilder buildFConstant(const DstOp &Res,
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| D | ConstantFoldingMIRBuilder.h | 28 MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
49 const DstOp &Dst = DstOps[0];
60 const DstOp &Dst = DstOps[0];
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 59 class DstOp {
68 DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {} in DstOp() function
69 DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {} in DstOp() function
70 DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {} in DstOp() function
71 DstOp(const LLT &T) : LLTTy(T), Ty(DstType::Ty_LLT) {} in DstOp() function
72 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {} in DstOp() function
381 MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size,
393 MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx);
405 MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV);
419 MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0,
[all …]
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| D | CSEMIRBuilder.h | 56 void profileDstOp(const DstOp &Op, GISelInstProfileBuilder &B) const;
58 void profileDstOps(ArrayRef<DstOp> Ops, GISelInstProfileBuilder &B) const { in profileDstOps()
59 for (const DstOp &Op : Ops) in profileDstOps()
72 void profileEverything(unsigned Opc, ArrayRef<DstOp> DstOps,
82 MachineInstrBuilder generateCopiesIfRequired(ArrayRef<DstOp> DstOps,
88 bool checkCopyToDefsPossible(ArrayRef<DstOp> DstOps);
94 MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
100 MachineInstrBuilder buildConstant(const DstOp &Res,
105 MachineInstrBuilder buildFConstant(const DstOp &Res,
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| D | ConstantFoldingMIRBuilder.h | 28 MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
49 const DstOp &Dst = DstOps[0];
60 const DstOp &Dst = DstOps[0];
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | CSEMIRBuilder.cpp | 65 void CSEMIRBuilder::profileDstOp(const DstOp &Op, in profileDstOp()
68 case DstOp::DstType::Ty_RC: in profileDstOp()
71 case DstOp::DstType::Ty_Reg: { in profileDstOp()
105 void CSEMIRBuilder::profileEverything(unsigned Opc, ArrayRef<DstOp> DstOps, in profileEverything()
129 bool CSEMIRBuilder::checkCopyToDefsPossible(ArrayRef<DstOp> DstOps) { in checkCopyToDefsPossible()
133 return std::all_of(DstOps.begin(), DstOps.end(), [](const DstOp &Op) { in checkCopyToDefsPossible()
134 DstOp::DstType DT = Op.getDstOpKind(); in checkCopyToDefsPossible()
135 return DT == DstOp::DstType::Ty_LLT || DT == DstOp::DstType::Ty_RC; in checkCopyToDefsPossible()
140 CSEMIRBuilder::generateCopiesIfRequired(ArrayRef<DstOp> DstOps, in generateCopiesIfRequired()
145 const DstOp &Op = DstOps[0]; in generateCopiesIfRequired()
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| D | MachineIRBuilder.cpp | 126 MachineInstrBuilder MachineIRBuilder::buildDynStackAlloc(const DstOp &Res, in buildDynStackAlloc()
137 MachineInstrBuilder MachineIRBuilder::buildFrameIndex(const DstOp &Res, in buildFrameIndex()
146 MachineInstrBuilder MachineIRBuilder::buildGlobalValue(const DstOp &Res, in buildGlobalValue()
182 MachineInstrBuilder MachineIRBuilder::buildPtrAdd(const DstOp &Res, in buildPtrAdd()
208 MachineInstrBuilder MachineIRBuilder::buildMaskLowPtrBits(const DstOp &Res, in buildMaskLowPtrBits()
238 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res, in buildCopy()
243 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res, in buildConstant()
264 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res, in buildConstant()
272 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res, in buildFConstant()
298 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res, in buildConstant()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | CSEMIRBuilder.cpp | 58 void CSEMIRBuilder::profileDstOp(const DstOp &Op, in profileDstOp()
61 case DstOp::DstType::Ty_RC: in profileDstOp()
90 void CSEMIRBuilder::profileEverything(unsigned Opc, ArrayRef<DstOp> DstOps, in profileEverything()
114 bool CSEMIRBuilder::checkCopyToDefsPossible(ArrayRef<DstOp> DstOps) { in checkCopyToDefsPossible()
118 return std::all_of(DstOps.begin(), DstOps.end(), [](const DstOp &Op) { in checkCopyToDefsPossible()
119 DstOp::DstType DT = Op.getDstOpKind(); in checkCopyToDefsPossible()
120 return DT == DstOp::DstType::Ty_LLT || DT == DstOp::DstType::Ty_RC; in checkCopyToDefsPossible()
125 CSEMIRBuilder::generateCopiesIfRequired(ArrayRef<DstOp> DstOps, in generateCopiesIfRequired()
130 const DstOp &Op = DstOps[0]; in generateCopiesIfRequired()
131 if (Op.getDstOpKind() == DstOp::DstType::Ty_Reg) in generateCopiesIfRequired()
[all …]
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| D | MachineIRBuilder.cpp | 163 MachineInstrBuilder MachineIRBuilder::buildDynStackAlloc(const DstOp &Res, in buildDynStackAlloc()
174 MachineInstrBuilder MachineIRBuilder::buildFrameIndex(const DstOp &Res, in buildFrameIndex()
183 MachineInstrBuilder MachineIRBuilder::buildGlobalValue(const DstOp &Res, in buildGlobalValue()
214 MachineInstrBuilder MachineIRBuilder::buildPtrAdd(const DstOp &Res, in buildPtrAdd()
240 MachineInstrBuilder MachineIRBuilder::buildPtrMask(const DstOp &Res, in buildPtrMask()
273 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res, in buildCopy()
278 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res, in buildConstant()
298 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res, in buildConstant()
306 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res, in buildFConstant()
331 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res, in buildConstant()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonRDFOpt.cpp | 121 const MachineOperand &DstOp = MI->getOperand(0); in INITIALIZE_PASS_DEPENDENCY() local
124 assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); in INITIALIZE_PASS_DEPENDENCY()
125 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_hi), in INITIALIZE_PASS_DEPENDENCY()
127 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_lo), in INITIALIZE_PASS_DEPENDENCY()
138 const MachineOperand &DstOp = MI->getOperand(0); in INITIALIZE_PASS_DEPENDENCY() local
140 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()), in INITIALIZE_PASS_DEPENDENCY()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRDFOpt.cpp | 121 const MachineOperand &DstOp = MI->getOperand(0); in INITIALIZE_PASS_DEPENDENCY() local
124 assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); in INITIALIZE_PASS_DEPENDENCY()
125 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_hi), in INITIALIZE_PASS_DEPENDENCY()
127 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_lo), in INITIALIZE_PASS_DEPENDENCY()
138 const MachineOperand &DstOp = MI->getOperand(0); in INITIALIZE_PASS_DEPENDENCY() local
140 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()), in INITIALIZE_PASS_DEPENDENCY()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRDFOpt.cpp | 105 const MachineOperand &DstOp = MI->getOperand(0); in interpretAsCopy() local
108 assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); in interpretAsCopy()
109 mapRegs({ DstOp.getReg(), Hexagon::subreg_hireg }, in interpretAsCopy()
111 mapRegs({ DstOp.getReg(), Hexagon::subreg_loreg }, in interpretAsCopy()
122 const MachineOperand &DstOp = MI->getOperand(0); in interpretAsCopy() local
124 mapRegs({ DstOp.getReg(), DstOp.getSubReg() }, in interpretAsCopy()
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| /external/llvm-project/llvm/lib/Linker/ |
| D | IRMover.cpp | 1233 MDNode *DstOp; in linkModuleFlagsMetadata() local
1235 std::tie(DstOp, DstIndex) = Flags.lookup(ID); in linkModuleFlagsMetadata()
1249 if (!DstOp) { in linkModuleFlagsMetadata()
1257 mdconst::extract<ConstantInt>(DstOp->getOperand(0)); in linkModuleFlagsMetadata()
1269 SrcOp->getOperand(2) != DstOp->getOperand(2)) in linkModuleFlagsMetadata()
1295 Metadata *FlagOps[] = {DstOp->getOperand(0), ID, New}; in linkModuleFlagsMetadata()
1305 SrcOp->getOperand(2) != DstOp->getOperand(2)) { in linkModuleFlagsMetadata()
1311 << *DstOp->getOperand(2) << "' from " << DstM.getModuleIdentifier() in linkModuleFlagsMetadata()
1319 mdconst::extract<ConstantInt>(DstOp->getOperand(2)); in linkModuleFlagsMetadata()
1326 (DstBehaviorValue != Module::Max ? SrcOp : DstOp)->getOperand(0), ID, in linkModuleFlagsMetadata()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Linker/ |
| D | IRMover.cpp | 1231 MDNode *DstOp; in linkModuleFlagsMetadata() local
1233 std::tie(DstOp, DstIndex) = Flags.lookup(ID); in linkModuleFlagsMetadata()
1247 if (!DstOp) { in linkModuleFlagsMetadata()
1255 mdconst::extract<ConstantInt>(DstOp->getOperand(0)); in linkModuleFlagsMetadata()
1267 SrcOp->getOperand(2) != DstOp->getOperand(2)) in linkModuleFlagsMetadata()
1293 Metadata *FlagOps[] = {DstOp->getOperand(0), ID, New}; in linkModuleFlagsMetadata()
1303 SrcOp->getOperand(2) != DstOp->getOperand(2)) { in linkModuleFlagsMetadata()
1309 << *DstOp->getOperand(2) << "' from " << DstM.getModuleIdentifier() in linkModuleFlagsMetadata()
1317 mdconst::extract<ConstantInt>(DstOp->getOperand(2)); in linkModuleFlagsMetadata()
1324 (DstBehaviorValue != Module::Max ? SrcOp : DstOp)->getOperand(0), ID, in linkModuleFlagsMetadata()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600ExpandSpecialInstrs.cpp | 100 MachineOperand &DstOp = MI.getOperand(DstIdx); in runOnMachineFunction() local
102 DstOp.getReg(), R600::OQAP); in runOnMachineFunction()
103 DstOp.setReg(R600::OQAP); in runOnMachineFunction()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | R600ExpandSpecialInstrs.cpp | 100 MachineOperand &DstOp = MI.getOperand(DstIdx); in runOnMachineFunction() local
102 DstOp.getReg(), R600::OQAP); in runOnMachineFunction()
103 DstOp.setReg(R600::OQAP); in runOnMachineFunction()
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| /external/llvm/lib/Linker/ |
| D | IRMover.cpp | 1049 MDNode *DstOp; in linkModuleFlagsMetadata() local
1051 std::tie(DstOp, DstIndex) = Flags.lookup(ID); in linkModuleFlagsMetadata()
1065 if (!DstOp) { in linkModuleFlagsMetadata()
1073 mdconst::extract<ConstantInt>(DstOp->getOperand(0)); in linkModuleFlagsMetadata()
1080 SrcOp->getOperand(2) != DstOp->getOperand(2)) in linkModuleFlagsMetadata()
1097 Metadata *FlagOps[] = {DstOp->getOperand(0), ID, New}; in linkModuleFlagsMetadata()
1110 if (SrcOp->getOperand(2) != DstOp->getOperand(2)) in linkModuleFlagsMetadata()
1117 if (SrcOp->getOperand(2) != DstOp->getOperand(2)) { in linkModuleFlagsMetadata()
1124 MDNode *DstValue = cast<MDNode>(DstOp->getOperand(2)); in linkModuleFlagsMetadata()
1136 MDNode *DstValue = cast<MDNode>(DstOp->getOperand(2)); in linkModuleFlagsMetadata()
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| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1155 static std::string getShuffleComment(const MachineOperand &DstOp, in getShuffleComment() argument
1171 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem"; in getShuffleComment()
1466 const MachineOperand &DstOp = MI->getOperand(0); in EmitInstruction() local
1474 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask)); in EmitInstruction()
1488 const MachineOperand &DstOp = MI->getOperand(0); in EmitInstruction() local
1496 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask)); in EmitInstruction()
1510 const MachineOperand &DstOp = MI->getOperand(0); in EmitInstruction() local
1518 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask)); in EmitInstruction()
1531 const MachineOperand &DstOp = MI->getOperand(0); in EmitInstruction() local
1551 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp1, SrcOp2, Mask)); in EmitInstruction()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ExpandSpecialInstrs.cpp | 85 MachineOperand &DstOp = MI.getOperand(DstIdx); in runOnMachineFunction() local
87 DstOp.getReg(), AMDGPU::OQAP); in runOnMachineFunction()
88 DstOp.setReg(AMDGPU::OQAP); in runOnMachineFunction()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrFoldTables.h | 70 uint16_t DstOp; member
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| D | X86MCInstLower.cpp | 1771 const MachineOperand &DstOp = MI->getOperand(0); in getShuffleComment() local
1775 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem"; in getShuffleComment()
2437 const MachineOperand &DstOp = MI->getOperand(0); in EmitInstruction() local
2438 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; in EmitInstruction()
2518 const MachineOperand &DstOp = MI->getOperand(0); in EmitInstruction() local
2519 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; in EmitInstruction()
2628 const MachineOperand &DstOp = MI->getOperand(0); in EmitInstruction() local
2629 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; in EmitInstruction()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86InstrFoldTables.h | 70 uint16_t DstOp; member
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| D | X86MCInstLower.cpp | 1804 const MachineOperand &DstOp = MI->getOperand(0); in getShuffleComment() local
1808 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem"; in getShuffleComment()
2168 const MachineOperand &DstOp = MI->getOperand(0); in addConstantComments() local
2169 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; in addConstantComments()
2247 const MachineOperand &DstOp = MI->getOperand(0); in addConstantComments() local
2248 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; in addConstantComments()
2356 const MachineOperand &DstOp = MI->getOperand(0); in addConstantComments() local
2357 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; in addConstantComments()
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | MIRYamlMapping.h | 449 unsigned DstOp;
452 return std::tie(SrcInst, SrcOp, DstInst, DstOp) ==
453 std::tie(Other.SrcInst, Other.SrcOp, Other.DstInst, Other.DstOp);
462 YamlIO.mapRequired("dstop", Sub.DstOp);
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