1 /* Copyright (c) 2007 Intel Corporation */
2 #include <stdio.h>
3 #include "internal.h"
4
5 /* Register Bit Masks */
6 /* Device Control */
7 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
8 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
9 #define E1000_CTRL_GIOMASTERD 0x00000008 /* GIO Master Disable*/
10 #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
11 #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
12 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
13 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
14 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
15 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
16 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
17 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
18 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
19 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
20 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
21 #define E1000_CTRL_SDP0_GPIEN 0x00010000 /* General Purpose Interrupt Detection Enable for SDP0 */
22 #define E1000_CTRL_SDP1_GPIEN 0x00020000 /* General Purpose Interrupt Detection Enable for SDP1 */
23 #define E1000_CTRL_SDP0_DATA 0x00040000 /* SDP0 Data */
24 #define E1000_CTRL_SDP1_DATA 0x00080000 /* SDP1 Data */
25 #define E1000_CTRL_ADVD3WUC 0x00100000 /* D3Cold WakeUp Capability Advertisement Enable */
26 #define E1000_CTRL_SDP0_WDE 0x00200000 /* Watchdog Indication for SDP0 */
27 #define E1000_CTRL_SDP1_IODIR 0x00400000 /* SDP1 Directionality */
28 #define E1000_CTRL_RST 0x04000000 /* Global reset */
29 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
30 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
31 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
32 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
33
34 /* Device Status */
35 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
36 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
37 #define E1000_STATUS_LANID 0x00000008 /* LAN ID */
38 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
39 #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
40 #define E1000_STATUS_SPEED_MASK 0x000000C0 /* Speed Mask */
41 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
42 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
43 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
44 #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
45 #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */
46 #define E1000_STATUS_GIOMASTEREN 0x00080000 /* GIO Master Enable Status */
47 #define E1000_STATUS_DMA_CGEN 0x80000000 /* DMA clock gating Enable */
48
49 /* Receive Control */
50 #define E1000_RCTL_EN 0x00000002 /* enable */
51 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */
52 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
53 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
54 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */
55 #define E1000_RCTL_LBM_MASK 0x000000C0 /* Loopback mode mask */
56 #define E1000_RCTL_LBM_NORM 0x00000000 /* normal loopback mode */
57 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
58 #define E1000_RCTL_LBM_SERDES 0x000000C0 /* SERDES loopback mode */
59 #define E1000_RCTL_RDMTS 0x00000300 /* rx desc min threshold size */
60 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
61 #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
62 #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
63 #define E1000_RCTL_MO 0x00003000 /* multicast offset shift */
64 #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 47:36 */
65 #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 46:35 */
66 #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 45:34 */
67 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 43:32 */
68 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
69 #define E1000_RCTL_BSIZE 0x00030000 /* rx buffer size */
70 #define E1000_RCTL_BSIZE_2048 0x00000000 /* rx buffer size 2048 */
71 #define E1000_RCTL_BSIZE_1024 0x00010000 /* rx buffer size 1024 */
72 #define E1000_RCTL_BSIZE_512 0x00020000 /* rx buffer size 512 */
73 #define E1000_RCTL_BSIZE_256 0x00030000 /* rx buffer size 256 */
74 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
75 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
76 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
77 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
78 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
79 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC from packet.0=No strip;1=strip */
80
81 /* Transmit Control */
82 #define E1000_TCTL_EN 0x00000002 /* enable tx */
83 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */
84 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
85 #define E1000_TCTL_BST 0x003ff000 /* Backoff Slot time */
86 #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
87 #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
88 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
89 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
90
igb_dump_regs(struct ethtool_drvinfo * info maybe_unused,struct ethtool_regs * regs)91 int igb_dump_regs(struct ethtool_drvinfo *info maybe_unused,
92 struct ethtool_regs *regs)
93 {
94 u32 *regs_buff = (u32 *)regs->data;
95 u32 reg;
96 u8 i;
97 u8 version = (u8)(regs->version >> 24);
98
99 if (version != 1)
100 return -1;
101
102 /* Device control register */
103 reg = regs_buff[0];
104 fprintf(stdout,
105 "0x00000: CTRL (Device control register) 0x%08X\n"
106 " Invert Loss-Of-Signal: %s\n"
107 " Receive flow control: %s\n"
108 " Transmit flow control: %s\n"
109 " VLAN mode: %s\n"
110 " Set link up: %s\n"
111 " D3COLD WakeUp capability advertisement: %s\n",
112 reg,
113 reg & E1000_CTRL_ILOS ? "yes" : "no",
114 reg & E1000_CTRL_RFCE ? "enabled" : "disabled",
115 reg & E1000_CTRL_TFCE ? "enabled" : "disabled",
116 reg & E1000_CTRL_VME ? "enabled" : "disabled",
117 reg & E1000_CTRL_SLU ? "1" : "0",
118 reg & E1000_CTRL_ADVD3WUC ? "enabled" : "disabled");
119 fprintf(stdout,
120 " Auto speed detect: %s\n"
121 " Speed select: %s\n"
122 " Force speed: %s\n"
123 " Force duplex: %s\n",
124 reg & E1000_CTRL_ASDE ? "enabled" : "disabled",
125 (reg & E1000_CTRL_SPD_SEL) == E1000_CTRL_SPD_10 ? "10Mb/s" :
126 (reg & E1000_CTRL_SPD_SEL) == E1000_CTRL_SPD_100 ? "100Mb/s" :
127 (reg & E1000_CTRL_SPD_SEL) == E1000_CTRL_SPD_1000 ? "1000Mb/s" :
128 "not used",
129 reg & E1000_CTRL_FRCSPD ? "yes" : "no",
130 reg & E1000_CTRL_FRCDPX ? "yes" : "no");
131
132 /* Device status register */
133 reg = regs_buff[1];
134 fprintf(stdout,
135 "0x00008: STATUS (Device status register) 0x%08X\n"
136 " Duplex: %s\n"
137 " Link up: %s\n"
138 " Transmission: %s\n"
139 " DMA clock gating: %s\n",
140 reg,
141 reg & E1000_STATUS_FD ? "full" : "half",
142 reg & E1000_STATUS_LU ? "link config" : "no link config",
143 reg & E1000_STATUS_TXOFF ? "paused" : "on",
144 reg & E1000_STATUS_DMA_CGEN ? "enabled" : "disabled");
145 fprintf(stdout,
146 " TBI mode: %s\n"
147 " Link speed: %s\n"
148 " Bus type: %s\n",
149 reg & E1000_STATUS_TBIMODE ? "enabled" : "disabled",
150 (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_10 ?
151 "10Mb/s" :
152 (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_100 ?
153 "100Mb/s" :
154 (reg & E1000_STATUS_SPEED_MASK) == E1000_STATUS_SPEED_1000 ?
155 "1000Mb/s" : "not used",
156 "PCI Express");
157
158 /* Receive control register */
159 reg = regs_buff[32];
160 fprintf(stdout,
161 "0x00100: RCTL (Receive control register) 0x%08X\n"
162 " Receiver: %s\n"
163 " Store bad packets: %s\n"
164 " Unicast promiscuous: %s\n"
165 " Multicast promiscuous: %s\n"
166 " Long packet: %s\n"
167 " Descriptor minimum threshold size: %s\n"
168 " Broadcast accept mode: %s\n"
169 " VLAN filter: %s\n"
170 " Cononical form indicator: %s\n"
171 " Discard pause frames: %s\n"
172 " Pass MAC control frames: %s\n"
173 " Loopback mode: %s\n",
174 reg,
175 reg & E1000_RCTL_EN ? "enabled" : "disabled",
176 reg & E1000_RCTL_SBP ? "enabled" : "disabled",
177 reg & E1000_RCTL_UPE ? "enabled" : "disabled",
178 reg & E1000_RCTL_MPE ? "enabled" : "disabled",
179 reg & E1000_RCTL_LPE ? "enabled" : "disabled",
180 (reg & E1000_RCTL_RDMTS) == E1000_RCTL_RDMTS_HALF ? "1/2" :
181 (reg & E1000_RCTL_RDMTS) == E1000_RCTL_RDMTS_QUAT ? "1/4" :
182 (reg & E1000_RCTL_RDMTS) == E1000_RCTL_RDMTS_EIGTH ? "1/8" :
183 "reserved",
184 reg & E1000_RCTL_BAM ? "accept" : "ignore",
185 reg & E1000_RCTL_VFE ? "enabled" : "disabled",
186 reg & E1000_RCTL_CFIEN ? "enabled" : "disabled",
187 reg & E1000_RCTL_DPF ? "ignored" : "filtered",
188 reg & E1000_RCTL_PMCF ? "pass" : "don't pass",
189 (reg & E1000_RCTL_LBM_MASK) == E1000_RCTL_LBM_NORM ? "normal" :
190 (reg & E1000_RCTL_LBM_MASK) == E1000_RCTL_LBM_MAC ? "MAC":
191 (reg & E1000_RCTL_LBM_MASK) == E1000_RCTL_LBM_SERDES ? "SERDES":
192 "undefined");
193 fprintf(stdout,
194 " Receive buffer size: %s\n",
195 (reg & E1000_RCTL_BSIZE)==E1000_RCTL_BSIZE_2048 ? "2048" :
196 (reg & E1000_RCTL_BSIZE)==E1000_RCTL_BSIZE_1024 ? "1024" :
197 (reg & E1000_RCTL_BSIZE)==E1000_RCTL_BSIZE_512 ? "512" :
198 "256");
199
200 /* Receive descriptor registers */
201 fprintf(stdout,
202 "0x02808: RDLEN (Receive desc length) 0x%08X\n",
203 regs_buff[137]);
204 fprintf(stdout,
205 "0x02810: RDH (Receive desc head) 0x%08X\n",
206 regs_buff[141]);
207 fprintf(stdout,
208 "0x02818: RDT (Receive desc tail) 0x%08X\n",
209 regs_buff[145]);
210
211 /* Transmit control register */
212 reg = regs_buff[38];
213 fprintf(stdout,
214 "0x00400: TCTL (Transmit ctrl register) 0x%08X\n"
215 " Transmitter: %s\n"
216 " Pad short packets: %s\n"
217 " Software XOFF Transmission: %s\n",
218 reg,
219 reg & E1000_TCTL_EN ? "enabled" : "disabled",
220 reg & E1000_TCTL_PSP ? "enabled" : "disabled",
221 reg & E1000_TCTL_SWXOFF ? "enabled" : "disabled");
222 fprintf(stdout,
223 " Re-transmit on late collision: %s\n",
224 reg & E1000_TCTL_RTLC ? "enabled" : "disabled");
225
226 /* Transmit descriptor registers */
227 fprintf(stdout,
228 "0x03808: TDLEN (Transmit desc length) 0x%08X\n",
229 regs_buff[219]);
230 fprintf(stdout,
231 "0x03810: TDH (Transmit desc head) 0x%08X\n",
232 regs_buff[223]);
233 fprintf(stdout,
234 "0x03818: TDT (Transmit desc tail) 0x%08X\n",
235 regs_buff[227]);
236
237
238 fprintf(stdout,
239 "0x00018: CTRL_EXT (Extended device control) 0x%08X\n",
240 regs_buff[2]);
241
242 fprintf(stdout,
243 "0x00018: MDIC (MDI control) 0x%08X\n",
244 regs_buff[3]);
245
246 fprintf(stdout,
247 "0x00024: SCTL (SERDES ANA) 0x%08X\n",
248 regs_buff[4]);
249
250 fprintf(stdout,
251 "0x00034: CONNSW (Copper/Fiber switch control) 0x%08X\n",
252 regs_buff[5]);
253
254 fprintf(stdout,
255 "0x00038: VET (VLAN Ether type) 0x%08X\n",
256 regs_buff[6]);
257
258 fprintf(stdout,
259 "0x00E00: LEDCTL (LED control) 0x%08X\n",
260 regs_buff[7]);
261
262 fprintf(stdout,
263 "0x01000: PBA (Packet buffer allocation) 0x%08X\n",
264 regs_buff[8]);
265
266 fprintf(stdout,
267 "0x01008: PBS (Packet buffer size) 0x%08X\n",
268 regs_buff[9]);
269
270 fprintf(stdout,
271 "0x01048: FRTIMER (Free running timer) 0x%08X\n",
272 regs_buff[10]);
273
274 fprintf(stdout,
275 "0x0104C: TCPTIMER (TCP timer) 0x%08X\n",
276 regs_buff[11]);
277
278 fprintf(stdout,
279 "0x00010: EEC (EEPROM/FLASH control) 0x%08X\n",
280 regs_buff[12]);
281
282 fprintf(stdout,
283 "0x01580: EICR (Extended interrupt cause) 0x%08X\n",
284 regs_buff[13]);
285
286 fprintf(stdout,
287 "0x01520: EICS (Extended interrupt cause set) 0x%08X\n",
288 regs_buff[14]);
289
290 fprintf(stdout,
291 "0x01524: EIMS (Extended interrup set/read) 0x%08X\n",
292 regs_buff[15]);
293
294 fprintf(stdout,
295 "0x01528: EIMC (Extended interrupt mask clear) 0x%08X\n",
296 regs_buff[16]);
297
298 fprintf(stdout,
299 "0x0152C: EIAC (Extended interrupt auto clear) 0x%08X\n",
300 regs_buff[17]);
301
302 fprintf(stdout,
303 "0x01530: EIAM (Extended interrupt auto mask) 0x%08X\n",
304 regs_buff[18]);
305
306 fprintf(stdout,
307 "0x01500: ICR (Interrupt cause read) 0x%08X\n",
308 regs_buff[19]);
309
310 fprintf(stdout,
311 "0x01504: ICS (Interrupt cause set) 0x%08X\n",
312 regs_buff[20]);
313
314 fprintf(stdout,
315 "0x01508: IMS (Interrupt mask set/read) 0x%08X\n",
316 regs_buff[21]);
317
318 fprintf(stdout,
319 "0x0150C: IMC (Interrupt mask clear) 0x%08X\n",
320 regs_buff[22]);
321
322 fprintf(stdout,
323 "0x04100: IAC (Interrupt assertion count) 0x%08X\n",
324 regs_buff[23]);
325
326 fprintf(stdout,
327 "0x01510: IAM (Interr acknowledge auto-mask) 0x%08X\n",
328 regs_buff[24]);
329
330 fprintf(stdout,
331 "0x05AC0: IMIRVP (Immed interr rx VLAN priority) 0x%08X\n",
332 regs_buff[25]);
333
334 fprintf(stdout,
335 "0x00028: FCAL (Flow control address low) 0x%08X\n",
336 regs_buff[26]);
337
338 fprintf(stdout,
339 "0x0002C: FCAH (Flow control address high) 0x%08X\n",
340 regs_buff[27]);
341
342 fprintf(stdout,
343 "0x00170: FCTTV (Flow control tx timer value) 0x%08X\n",
344 regs_buff[28]);
345
346 fprintf(stdout,
347 "0x02160: FCRTL (Flow control rx threshold low) 0x%08X\n",
348 regs_buff[29]);
349
350 fprintf(stdout,
351 "0x02168: FCRTH (Flow control rx threshold high) 0x%08X\n",
352 regs_buff[30]);
353
354 fprintf(stdout,
355 "0x02460: FCRTV (Flow control refresh threshold) 0x%08X\n",
356 regs_buff[31]);
357
358 fprintf(stdout,
359 "0x05000: RXCSUM (Receive checksum control) 0x%08X\n",
360 regs_buff[33]);
361
362 fprintf(stdout,
363 "0x05004: RLPML (Receive long packet max length) 0x%08X\n",
364 regs_buff[34]);
365
366 fprintf(stdout,
367 "0x05008: RFCTL (Receive filter control) 0x%08X\n",
368 regs_buff[35]);
369
370 fprintf(stdout,
371 "0x05818: MRQC (Multiple rx queues command) 0x%08X\n",
372 regs_buff[36]);
373
374 fprintf(stdout,
375 "0x0581C: VMD_CTL (VMDq control) 0x%08X\n",
376 regs_buff[37]);
377
378 fprintf(stdout,
379 "0x00404: TCTL_EXT (Transmit control extended) 0x%08X\n",
380 regs_buff[39]);
381
382 fprintf(stdout,
383 "0x00410: TIPG (Transmit IPG) 0x%08X\n",
384 regs_buff[40]);
385
386 fprintf(stdout,
387 "0x03590: DTXCTL (DMA tx control) 0x%08X\n",
388 regs_buff[41]);
389
390 fprintf(stdout,
391 "0x05800: WUC (Wake up control) 0x%08X\n",
392 regs_buff[42]);
393
394 fprintf(stdout,
395 "0x05808: WUFC (Wake up filter control) 0x%08X\n",
396 regs_buff[43]);
397
398 fprintf(stdout,
399 "0x05810: WUS (Wake up status) 0x%08X\n",
400 regs_buff[44]);
401
402 fprintf(stdout,
403 "0x05838: IPAV (IP address valid) 0x%08X\n",
404 regs_buff[45]);
405
406 fprintf(stdout,
407 "0x05900: WUPL (Wake up packet length) 0x%08X\n",
408 regs_buff[46]);
409
410 fprintf(stdout,
411 "0x04200: PCS_CFG (PCS configuration 0) 0x%08X\n",
412 regs_buff[47]);
413
414 fprintf(stdout,
415 "0x04208: PCS_LCTL (PCS link control) 0x%08X\n",
416 regs_buff[48]);
417
418 fprintf(stdout,
419 "0x0420C: PCS_LSTS (PCS link status) 0x%08X\n",
420 regs_buff[49]);
421
422 fprintf(stdout,
423 "0x04218: PCS_ANADV (AN advertisement) 0x%08X\n",
424 regs_buff[50]);
425
426 fprintf(stdout,
427 "0x0421C: PCS_LPAB (Link partner ability) 0x%08X\n",
428 regs_buff[51]);
429
430 fprintf(stdout,
431 "0x04220: PCS_NPTX (Next Page transmit) 0x%08X\n",
432 regs_buff[52]);
433
434 fprintf(stdout,
435 "0x04224: PCS_LPABNP (Link partner ability Next Page) 0x%08X\n",
436 regs_buff[53]);
437
438 fprintf(stdout,
439 "0x04000: CRCERRS (CRC error count) 0x%08X\n",
440 regs_buff[54]);
441
442 fprintf(stdout,
443 "0x04004: ALGNERRC (Alignment error count) 0x%08X\n",
444 regs_buff[55]);
445
446 fprintf(stdout,
447 "0x04008: SYMERRS (Symbol error count) 0x%08X\n",
448 regs_buff[56]);
449
450 fprintf(stdout,
451 "0x0400C: RXERRC (RX error count) 0x%08X\n",
452 regs_buff[57]);
453
454 fprintf(stdout,
455 "0x04010: MPC (Missed packets count) 0x%08X\n",
456 regs_buff[58]);
457
458 fprintf(stdout,
459 "0x04014: SCC (Single collision count) 0x%08X\n",
460 regs_buff[59]);
461
462 fprintf(stdout,
463 "0x04018: ECOL (Excessive collisions count) 0x%08X\n",
464 regs_buff[60]);
465
466 fprintf(stdout,
467 "0x0401C: MCC (Multiple collision count) 0x%08X\n",
468 regs_buff[61]);
469
470 fprintf(stdout,
471 "0x04020: LATECOL (Late collisions count) 0x%08X\n",
472 regs_buff[62]);
473
474 fprintf(stdout,
475 "0x04028: COLC (Collision count) 0x%08X\n",
476 regs_buff[63]);
477
478 fprintf(stdout,
479 "0x04030: DC (Defer count) 0x%08X\n",
480 regs_buff[64]);
481
482 fprintf(stdout,
483 "0x04034: TNCRS (Transmit with no CRS) 0x%08X\n",
484 regs_buff[65]);
485
486 fprintf(stdout,
487 "0x04038: SEC (Sequence error count) 0x%08X\n",
488 regs_buff[66]);
489
490 fprintf(stdout,
491 "0x0403C: HTDPMC (Host tx discrd pkts MAC count) 0x%08X\n",
492 regs_buff[67]);
493
494 fprintf(stdout,
495 "0x04040: RLEC (Receive length error count) 0x%08X\n",
496 regs_buff[68]);
497
498 fprintf(stdout,
499 "0x04048: XONRXC (XON received count) 0x%08X\n",
500 regs_buff[69]);
501
502 fprintf(stdout,
503 "0x0404C: XONTXC (XON transmitted count) 0x%08X\n",
504 regs_buff[70]);
505
506 fprintf(stdout,
507 "0x04050: XOFFRXC (XOFF received count) 0x%08X\n",
508 regs_buff[71]);
509
510 fprintf(stdout,
511 "0x04054: XOFFTXC (XOFF transmitted count) 0x%08X\n",
512 regs_buff[72]);
513
514 fprintf(stdout,
515 "0x04058: FCRUC (FC received unsupported count) 0x%08X\n",
516 regs_buff[73]);
517
518 fprintf(stdout,
519 "0x0405C: PRC64 (Packets rx (64 B) count) 0x%08X\n",
520 regs_buff[74]);
521
522 fprintf(stdout,
523 "0x04060: PRC127 (Packets rx (65-127 B) count) 0x%08X\n",
524 regs_buff[75]);
525
526 fprintf(stdout,
527 "0x04064: PRC255 (Packets rx (128-255 B) count) 0x%08X\n",
528 regs_buff[76]);
529
530 fprintf(stdout,
531 "0x04068: PRC511 (Packets rx (256-511 B) count) 0x%08X\n",
532 regs_buff[77]);
533
534 fprintf(stdout,
535 "0x0406C: PRC1023 (Packets rx (512-1023 B) count) 0x%08X\n",
536 regs_buff[78]);
537
538 fprintf(stdout,
539 "0x04070: PRC1522 (Packets rx (1024-max B) count) 0x%08X\n",
540 regs_buff[79]);
541
542 fprintf(stdout,
543 "0x04074: GPRC (Good packets received count) 0x%08X\n",
544 regs_buff[80]);
545
546 fprintf(stdout,
547 "0x04078: BPRC (Broadcast packets rx count) 0x%08X\n",
548 regs_buff[81]);
549
550 fprintf(stdout,
551 "0x0407C: MPRC (Multicast packets rx count) 0x%08X\n",
552 regs_buff[82]);
553
554 fprintf(stdout,
555 "0x04080: GPTC (Good packets tx count) 0x%08X\n",
556 regs_buff[83]);
557
558 fprintf(stdout,
559 "0x04088: GORCL (Good octets rx count lower) 0x%08X\n",
560 regs_buff[84]);
561
562 fprintf(stdout,
563 "0x0408C: GORCH (Good octets rx count upper) 0x%08X\n",
564 regs_buff[85]);
565
566 fprintf(stdout,
567 "0x04090: GOTCL (Good octets tx count lower) 0x%08X\n",
568 regs_buff[86]);
569
570 fprintf(stdout,
571 "0x04094: GOTCH (Good octets tx count upper) 0x%08X\n",
572 regs_buff[87]);
573
574 fprintf(stdout,
575 "0x040A0: RNBC (Receive no buffers count) 0x%08X\n",
576 regs_buff[88]);
577
578 fprintf(stdout,
579 "0x040A4: RUC (Receive undersize count) 0x%08X\n",
580 regs_buff[89]);
581
582 fprintf(stdout,
583 "0x040A8: RFC (Receive fragment count) 0x%08X\n",
584 regs_buff[90]);
585
586 fprintf(stdout,
587 "0x040AC: ROC (Receive oversize count) 0x%08X\n",
588 regs_buff[91]);
589
590 fprintf(stdout,
591 "0x040B0: RJC (Receive jabber count) 0x%08X\n",
592 regs_buff[92]);
593
594 fprintf(stdout,
595 "0x040B4: MGPRC (Management packets rx count) 0x%08X\n",
596 regs_buff[93]);
597
598 fprintf(stdout,
599 "0x040B8: MGPDC (Management pkts dropped count) 0x%08X\n",
600 regs_buff[94]);
601
602 fprintf(stdout,
603 "0x040BC: MGPTC (Management packets tx count) 0x%08X\n",
604 regs_buff[95]);
605
606 fprintf(stdout,
607 "0x040C0: TORL (Total octets received lower) 0x%08X\n",
608 regs_buff[96]);
609
610 fprintf(stdout,
611 "0x040C4: TORH (Total octets received upper) 0x%08X\n",
612 regs_buff[97]);
613
614 fprintf(stdout,
615 "0x040C8: TOTL (Total octets transmitted lower) 0x%08X\n",
616 regs_buff[98]);
617
618 fprintf(stdout,
619 "0x040CC: TOTH (Total octets transmitted upper) 0x%08X\n",
620 regs_buff[99]);
621
622 fprintf(stdout,
623 "0x040D0: TPR (Total packets received) 0x%08X\n",
624 regs_buff[100]);
625
626 fprintf(stdout,
627 "0x040D4: TPT (Total packets transmitted) 0x%08X\n",
628 regs_buff[101]);
629
630 fprintf(stdout,
631 "0x040D8: PTC64 (Packets tx (64 B) count) 0x%08X\n",
632 regs_buff[102]);
633
634 fprintf(stdout,
635 "0x040DC: PTC127 (Packets tx (65-127 B) count) 0x%08X\n",
636 regs_buff[103]);
637
638 fprintf(stdout,
639 "0x040E0: PTC255 (Packets tx (128-255 B) count) 0x%08X\n",
640 regs_buff[104]);
641
642 fprintf(stdout,
643 "0x040E4: PTC511 (Packets tx (256-511 B) count) 0x%08X\n",
644 regs_buff[105]);
645
646 fprintf(stdout,
647 "0x040E8: PTC1023 (Packets tx (512-1023 B) count) 0x%08X\n",
648 regs_buff[106]);
649
650 fprintf(stdout,
651 "0x040EC: PTC1522 (Packets tx (> 1024 B) count) 0x%08X\n",
652 regs_buff[107]);
653
654 fprintf(stdout,
655 "0x040F0: MPTC (Multicast packets tx count) 0x%08X\n",
656 regs_buff[108]);
657
658 fprintf(stdout,
659 "0x040F4: BPTC (Broadcast packets tx count) 0x%08X\n",
660 regs_buff[109]);
661
662 fprintf(stdout,
663 "0x040F8: TSCTC (TCP segment context tx count) 0x%08X\n",
664 regs_buff[110]);
665
666 fprintf(stdout,
667 "0x04100: IAC (Interrupt assertion count) 0x%08X\n",
668 regs_buff[111]);
669
670 fprintf(stdout,
671 "0x04104: RPTHC (Rx packets to host count) 0x%08X\n",
672 regs_buff[112]);
673
674 fprintf(stdout,
675 "0x04118: HGPTC (Host good packets tx count) 0x%08X\n",
676 regs_buff[113]);
677
678 fprintf(stdout,
679 "0x04128: HGORCL (Host good octets rx cnt lower) 0x%08X\n",
680 regs_buff[114]);
681
682 fprintf(stdout,
683 "0x0412C: HGORCH (Host good octets rx cnt upper) 0x%08X\n",
684 regs_buff[115]);
685
686 fprintf(stdout,
687 "0x04130: HGOTCL (Host good octets tx cnt lower) 0x%08X\n",
688 regs_buff[116]);
689
690 fprintf(stdout,
691 "0x04134: HGOTCH (Host good octets tx cnt upper) 0x%08X\n",
692 regs_buff[117]);
693
694 fprintf(stdout,
695 "0x04138: LENNERS (Length error count) 0x%08X\n",
696 regs_buff[118]);
697
698 fprintf(stdout,
699 "0x04228: SCVPC (SerDes/SGMII code viol pkt cnt) 0x%08X\n",
700 regs_buff[119]);
701
702 fprintf(stdout,
703 "0x0A018: HRMPC (Header redir missed pkt count) 0x%08X\n",
704 regs_buff[120]);
705
706 for (i = 0; i < 4; i++)
707 fprintf(stdout,
708 "0x0%02X: SRRCTL%d (Split and replic rx ctl%d) 0x%08X\n",
709 0x0280C + (0x100 * i), i, i, regs_buff[121 + i]);
710
711 for (i = 0; i < 4; i++)
712 fprintf(stdout,
713 "0x0%02X: PSRTYPE%d (Packet split receive type%d) 0x%08X\n",
714 0x05480 + (0x4 * i), i, i, regs_buff[125 + i]);
715
716 for (i = 0; i < 4; i++)
717 fprintf(stdout,
718 "0x0%02X: RDBAL%d (Rx desc base addr low%d) 0x%08X\n",
719 0x02800 + (0x100 * i), i, i, regs_buff[129 + i]);
720
721 for (i = 0; i < 4; i++)
722 fprintf(stdout,
723 "0x0%02X: RDBAH%d (Rx desc base addr high%d) 0x%08X\n",
724 0x02804 + (0x100 * i), i, i, regs_buff[133 + i]);
725
726 for (i = 0; i < 4; i++)
727 fprintf(stdout,
728 "0x0%02X: RDLEN%d (Rx descriptor length%d) 0x%08X\n",
729 0x02808 + (0x100 * i), i, i, regs_buff[137 + i]);
730
731 for (i = 0; i < 4; i++)
732 fprintf(stdout,
733 "0x0%02X: RDH%d (Rx descriptor head%d) 0x%08X\n",
734 0x02810 + (0x100 * i), i, i, regs_buff[141 + i]);
735
736 for (i = 0; i < 4; i++)
737 fprintf(stdout,
738 "0x0%02X: RDT%d (Rx descriptor tail%d) 0x%08X\n",
739 0x02818 + (0x100 * i), i, i, regs_buff[145 + i]);
740
741 for (i = 0; i < 4; i++)
742 fprintf(stdout,
743 "0x0%02X: RXDCTL%d (Rx descriptor control%d) 0x%08X\n",
744 0x02828 + (0x100 * i), i, i, regs_buff[149 + i]);
745
746 for (i = 0; i < 10; i++)
747 fprintf(stdout,
748 "0x0%02X: EITR%d (Interrupt throttle%d) 0x%08X\n",
749 0x01680 + (0x4 * i), i, i, regs_buff[153 + i]);
750
751 for (i = 0; i < 8; i++)
752 fprintf(stdout,
753 "0x0%02X: IMIR%d (Immediate interrupt Rx%d) 0x%08X\n",
754 0x05A80 + (0x4 * i), i, i, regs_buff[163 + i]);
755
756 for (i = 0; i < 8; i++)
757 fprintf(stdout,
758 "0x0%02X: IMIREXT%d (Immediate interr Rx extended%d) 0x%08X\n",
759 0x05AA0 + (0x4 * i), i, i, regs_buff[171 + i]);
760
761 for (i = 0; i < 16; i++)
762 fprintf(stdout,
763 "0x0%02X: RAL%02d (Receive address low%02d) 0x%08X\n",
764 0x05400 + (0x8 * i), i,i, regs_buff[179 + i]);
765
766 for (i = 0; i < 16; i++)
767 fprintf(stdout,
768 "0x0%02X: RAH%02d (Receive address high%02d) 0x%08X\n",
769 0x05404 + (0x8 * i), i, i, regs_buff[195 + i]);
770
771 for (i = 0; i < 4; i++)
772 fprintf(stdout,
773 "0x0%02X: TDBAL%d (Tx desc base address low%d) 0x%08X\n",
774 0x03800 + (0x100 * i), i, i, regs_buff[211 + i]);
775
776 for (i = 0; i < 4; i++)
777 fprintf(stdout,
778 "0x0%02X: TDBAH%d (Tx desc base address high%d) 0x%08X\n",
779 0x03804 + (0x100 * i), i, i, regs_buff[215 + i]);
780
781 for (i = 0; i < 4; i++)
782 fprintf(stdout,
783 "0x0%02X: TDLEN%d (Tx descriptor length%d) 0x%08X\n",
784 0x03808 + (0x100 * i), i, i, regs_buff[219 + i]);
785
786 for (i = 0; i < 4; i++)
787 fprintf(stdout,
788 "0x0%02X: TDH%d (Transmit descriptor head%d) 0x%08X\n",
789 0x03810 + (0x100 * i), i, i, regs_buff[223 + i]);
790
791 for (i = 0; i < 4; i++)
792 fprintf(stdout,
793 "0x0%02X: TDT%d (Transmit descriptor tail%d) 0x%08X\n",
794 0x03818 + (0x100 * i), i, i, regs_buff[227 + i]);
795
796 for (i = 0; i < 4; i++)
797 fprintf(stdout,
798 "0x0%02X: TXDCTL%d (Transmit descriptor control%d) 0x%08X\n",
799 0x03828 + (0x100 * i), i, i, regs_buff[231 + i]);
800
801 for (i = 0; i < 4; i++)
802 fprintf(stdout,
803 "0x0%02X: TDWBAL%d (Tx desc complete wb addr low%d) 0x%08X\n",
804 0x03838 + (0x100 * i), i, i, regs_buff[235 + i]);
805
806 for (i = 0; i < 4; i++)
807 fprintf(stdout,
808 "0x0%02X: TDWBAH%d (Tx desc complete wb addr hi%d) 0x%08X\n",
809 0x0383C + (0x100 * i), i, i, regs_buff[239 + i]);
810
811 for (i = 0; i < 4; i++)
812 fprintf(stdout,
813 "0x0%02X: DCA_TXCTRL%d (Tx DCA control%d) 0x%08X\n",
814 0x03814 + (0x100 * i), i, i, regs_buff[243 + i]);
815
816 for (i = 0; i < 4; i++)
817 fprintf(stdout,
818 "0x0%02X: IP4AT%d (IPv4 address table%d) 0x%08X\n",
819 0x05840 + (0x8 * i), i, i, regs_buff[247 + i]);
820
821 for (i = 0; i < 4; i++)
822 fprintf(stdout,
823 "0x0%02X: IP6AT%d (IPv6 address table%d) 0x%08X\n",
824 0x05880 + (0x4 * i), i, i, regs_buff[251 + i]);
825
826 for (i = 0; i < 32; i++)
827 fprintf(stdout,
828 "0x0%02X: WUPM%02d (Wake up packet memory%02d) 0x%08X\n",
829 0x05A00 + (0x4 * i), i, i, regs_buff[255 + i]);
830
831 for (i = 0; i < 128; i++)
832 fprintf(stdout,
833 "0x0%02X: FFMT%03d (Flexible filter mask table%03d) 0x%08X\n",
834 0x09000 + (0x8 * i), i, i, regs_buff[287 + i]);
835
836 for (i = 0; i < 128; i++)
837 fprintf(stdout,
838 "0x0%02X: FFVT%03d (Flexible filter value table%03d) 0x%08X\n",
839 0x09800 + (0x8 * i), i, i, regs_buff[415 + i]);
840
841 for (i = 0; i < 4; i++)
842 fprintf(stdout,
843 "0x0%02X: FFLT%d (Flexible filter length table%d) 0x%08X\n",
844 0x05F00 + (0x8 * i), i, i, regs_buff[543 + i]);
845
846 fprintf(stdout,
847 "0x03410: TDFH (Tx data FIFO head) 0x%08X\n",
848 regs_buff[547]);
849
850 fprintf(stdout,
851 "0x03418: TDFT (Tx data FIFO tail) 0x%08X\n",
852 regs_buff[548]);
853
854 fprintf(stdout,
855 "0x03420: TDFHS (Tx data FIFO head saved) 0x%08X\n",
856 regs_buff[549]);
857
858 fprintf(stdout,
859 "0x03430: TDFPC (Tx data FIFO packet count) 0x%08X\n",
860 regs_buff[550]);
861
862 /*
863 * Starting from kernel version 5.3 the registers dump buffer grew from
864 * 739 4-byte words to 740 words, and word 740 contains the RR2DCDELAY
865 * register.
866 */
867 if (regs->len < 740)
868 return 0;
869
870 fprintf(stdout,
871 "0x05BF4: RR2DCDELAY (Max. DMA read delay) 0x%08X\n",
872 regs_buff[739]);
873
874 return 0;
875 }
876
877