| /external/llvm-project/llvm/test/MC/ARM/ |
| D | thumb2-narrow-dp.ll | 193 EORS r0, r2, r1 // Must be wide - 3 distinct registers
194 EORS r5, r5, r1 // Should choose narrow
195 EORS r5, r1, r5 // Should choose narrow - commutative
196 EORS.W r0, r0, r1 // Explicitly wide
197 EORS.W r2, r1, r2
199 EORS r7, r7, r1 // Should use narrow
200 EORS r7, r1, r7 // Commutative
201 EORS r8, r1, r8 // high registers so must use wide encoding
202 EORS r8, r8, r1
203 EORS r6, r8, r6
[all …]
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| /external/llvm/test/MC/ARM/ |
| D | thumb2-narrow-dp.ll | 193 EORS r0, r2, r1 // Must be wide - 3 distinct registers
194 EORS r5, r5, r1 // Should choose narrow
195 EORS r5, r1, r5 // Should choose narrow - commutative
196 EORS.W r0, r0, r1 // Explicitly wide
197 EORS.W r2, r1, r2
199 EORS r7, r7, r1 // Should use narrow
200 EORS r7, r1, r7 // Commutative
201 EORS r8, r1, r8 // high registers so must use wide encoding
202 EORS r8, r8, r1
203 EORS r6, r8, r6
[all …]
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| /external/vixl/test/aarch32/config/ |
| D | cond-rd-rn-operand-const-a32.json | 41 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
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| D | cond-rd-rn-operand-rm-t32.json | 78 "Eors", // EORS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
79 // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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| D | cond-rd-rn-operand-rm-shift-rs-a32.json | 38 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
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| D | cond-rd-rn-operand-const-t32.json | 47 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
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| D | cond-rd-rn-operand-rm-shift-amount-1to31-a32.json | 40 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
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| D | cond-rd-rn-operand-rm-shift-amount-1to32-a32.json | 40 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
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| D | cond-rd-rn-operand-rm-shift-amount-1to32-t32.json | 44 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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| D | cond-rd-rn-operand-rm-shift-amount-1to31-t32.json | 44 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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| D | cond-rd-rn-operand-rm-a32.json | 49 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_T2_32.c | 126 #define EORS 0x4040 macro
845 return push_inst16(compiler, EORS | RD3(dst) | RN3(arg2)); in emit_op_imm()
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| /external/OpenCSD/decoder/tests/snapshots/TC2/ds5-dumps/ |
| D | etmv3_0x10.txt | 2297 Instruction 2165 S:0xC00422CA 0x4070 1 EORS r0,r0,r6 false
2298 Instruction 2166 S:0xC00422CC 0x4071 1 EORS r1,r1,r6 false
2718 Instruction 2572 S:0xC00176E2 0x4060 2 EORS r0,r0,r4 false
2719 Instruction 2573 S:0xC00176E4 0x4069 1 EORS r1,r1,r5 false
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| D | etmv3_0x11.txt | 5486 Instruction 5310 S:0xC00422CA 0x4070 1 EORS r0,r0,r6 false
5487 Instruction 5311 S:0xC00422CC 0x4071 1 EORS r1,r1,r6 false
6936 Instruction 6713 S:0xC00422CA 0x4070 1 EORS r0,r0,r6 false
6937 Instruction 6714 S:0xC00422CC 0x4071 1 EORS r1,r1,r6 false
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| D | ptmv1_0x13.txt | 7488 Instruction 7221 S:0xC00422CA 0x4070 0 EORS r0,r0,r6 false
7489 Instruction 7222 S:0xC00422CC 0x4071 0 EORS r1,r1,r6 false
9529 Instruction 9220 S:0xC00422CA 0x4070 0 EORS r0,r0,r6 false
9530 Instruction 9221 S:0xC00422CC 0x4071 0 EORS r1,r1,r6 false
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