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Searched refs:EXTRACT_VECTOR_ELT (Results 1 – 25 of 117) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp209 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom); in R600TargetLowering()
210 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom); in R600TargetLowering()
211 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); in R600TargetLowering()
212 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); in R600TargetLowering()
279 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in R600TargetLowering()
480 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
573 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
575 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
577 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
579 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
[all …]
DSIISelLowering.cpp270 case ISD::EXTRACT_VECTOR_ELT: in SITargetLowering()
297 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
298 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32); in SITargetLowering()
322 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom); in SITargetLowering()
323 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom); in SITargetLowering()
324 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i8, Custom); in SITargetLowering()
325 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i8, Custom); in SITargetLowering()
326 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i8, Custom); in SITargetLowering()
332 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i16, Custom); in SITargetLowering()
333 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f16, Custom); in SITargetLowering()
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/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp209 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom); in R600TargetLowering()
210 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom); in R600TargetLowering()
211 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); in R600TargetLowering()
212 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); in R600TargetLowering()
279 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in R600TargetLowering()
480 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
573 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
575 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
577 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
579 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
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DSIISelLowering.cpp302 case ISD::EXTRACT_VECTOR_ELT: in SITargetLowering()
329 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
330 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32); in SITargetLowering()
343 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
344 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v8i32); in SITargetLowering()
357 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
358 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v16i32); in SITargetLowering()
371 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
372 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v32i32); in SITargetLowering()
396 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom); in SITargetLowering()
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/external/llvm-project/llvm/test/CodeGen/SystemZ/
DDAGCombine_trunc_extract.ll4 ; when handling EXTRACT_VECTOR_ELT without vector support.
Ddag-combine-03.ll7 ; The EXTRACT_VECTOR_ELT is done first into an i32, and then AND:ed with
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp166 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom); in R600TargetLowering()
167 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom); in R600TargetLowering()
168 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); in R600TargetLowering()
169 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); in R600TargetLowering()
197 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in R600TargetLowering()
617 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
743 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
745 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
747 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
749 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
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DSIISelLowering.cpp146 case ISD::EXTRACT_VECTOR_ELT: in SITargetLowering()
168 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
169 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32); in SITargetLowering()
970 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, OutVals[i], in LowerReturn()
1829 SDValue I = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ, in LowerINTRINSIC_WO_CHAIN()
1831 SDValue J = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ, in LowerINTRINSIC_WO_CHAIN()
2100 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero); in LowerSELECT()
2101 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero); in LowerSELECT()
2105 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One); in LowerSELECT()
2106 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One); in LowerSELECT()
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DAMDGPUISelLowering.cpp1036 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in split64BitValue()
1037 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in split64BitValue()
1047 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in getLoHalf64()
1055 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in getHiHalf64()
1144 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value, in MergeVectorStore()
1656 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One); in LowerFTRUNC()
1770 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One); in LowerFROUND64()
1862 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in LowerCTLZ()
1863 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in LowerCTLZ()
1995 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, in LowerINT_TO_FP64()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp297 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in ScalarizeVecRes_EXTRACT_SUBVECTOR()
361 ISD::EXTRACT_VECTOR_ELT, DL, VT, Op, in ScalarizeVecRes_UnaryOp()
387 ISD::EXTRACT_VECTOR_ELT, DL, OpEltVT, Op, in ScalarizeVecRes_VecInregOp()
425 ISD::EXTRACT_VECTOR_ELT, DL, VT, Cond, in ScalarizeVecRes_VSELECT()
527 ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS, in ScalarizeVecRes_SETCC()
530 ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS, in ScalarizeVecRes_SETCC()
586 case ISD::EXTRACT_VECTOR_ELT: in ScalarizeVectorOperand()
1336 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, OperandEltVT, Operand, in UnrollVectorOp_StrictFP()
1855 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Inputs[Input], in SplitVecRes_VECTOR_SHUFFLE()
1928 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break; in SplitVectorOperand()
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DLegalizeTypesGeneric.cpp123 ISD::EXTRACT_VECTOR_ELT, dl, ElemVT, CastInOp, in ExpandRes_BITCAST()
233 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
237 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp194 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in ScalarizeVecRes_EXTRACT_SUBVECTOR()
262 ISD::EXTRACT_VECTOR_ELT, DL, VT, Op, in ScalarizeVecRes_UnaryOp()
396 ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS, in ScalarizeVecRes_VSETCC()
399 ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS, in ScalarizeVecRes_VSETCC()
449 case ISD::EXTRACT_VECTOR_ELT: in ScalarizeVectorOperand()
1407 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Inputs[Input], in SplitVecRes_VECTOR_SHUFFLE()
1462 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break; in SplitVectorOperand()
1647 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vec, in SplitVecOp_EXTRACT_VECTOR_ELT()
1918 ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Op, in SplitVecOp_CONCAT_VECTORS()
2260 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp1, in WidenVecRes_BinaryCanTrap()
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DLegalizeTypesGeneric.cpp130 ISD::EXTRACT_VECTOR_ELT, dl, ElemVT, CastInOp, in ExpandRes_BITCAST()
245 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
249 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp310 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in ScalarizeVecRes_EXTRACT_SUBVECTOR()
372 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op, in ScalarizeVecRes_UnaryOp()
397 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, OpEltVT, Op, in ScalarizeVecRes_VecInregOp()
434 Cond = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Cond, in ScalarizeVecRes_VSELECT()
535 LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS, in ScalarizeVecRes_SETCC()
537 RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS, in ScalarizeVecRes_SETCC()
592 case ISD::EXTRACT_VECTOR_ELT: in ScalarizeVectorOperand()
1441 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, OperandEltVT, in UnrollVectorOp_StrictFP()
1992 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, in SplitVecRes_VECTOR_SHUFFLE()
2065 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break; in SplitVectorOperand()
[all …]
DLegalizeTypesGeneric.cpp125 Vals.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ElemVT, in ExpandRes_BITCAST()
239 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
243 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h280 EXTRACT_VECTOR_ELT, enumerator
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h393 EXTRACT_VECTOR_ELT, enumerator
/external/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h505 EXTRACT_VECTOR_ELT, enumerator
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp155 for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT}) { in WebAssemblyTargetLowering()
1017 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
1279 if (Op.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in LowerSIGN_EXTEND_INREG()
1299 ISD::EXTRACT_VECTOR_ELT, DL, Extract.getValueType(), in LowerSIGN_EXTEND_INREG()
1337 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
1344 if (Index->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp100 setOperationAction(ISD::EXTRACT_VECTOR_ELT, T, Custom); in initializeHVXLowering()
191 setOperationAction(ISD::EXTRACT_VECTOR_ELT, BoolV, Custom); in initializeHVXLowering()
426 if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in buildHvxVectorReg()
1076 if (V.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in LowerHvxConcatVectors()
1078 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NTy, in LowerHvxConcatVectors()
1568 case ISD::EXTRACT_VECTOR_ELT: return LowerHvxExtractElement(Op, DAG); in LowerHvxOperation()
/external/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp157 for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT}) in WebAssemblyTargetLowering()
1204 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
1527 if (Op.getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerSIGN_EXTEND_INREG()
1552 ISD::EXTRACT_VECTOR_ELT, DL, Extract.getValueType(), in LowerSIGN_EXTEND_INREG()
1587 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
1594 if (Index->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
/external/llvm/lib/Target/PowerPC/
DPPCTargetTransformInfo.cpp346 if (ISD == ISD::EXTRACT_VECTOR_ELT || in getVectorInstrCost()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp389 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom); in NVPTXTargetLowering()
1901 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp, in LowerCONCAT_VECTORS()
1949 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector, in LowerEXTRACT_VECTOR_ELT()
1951 SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector, in LowerEXTRACT_VECTOR_ELT()
2187 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
2375 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val, in LowerSTOREVector()
2377 SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val, in LowerSTOREVector()
2385 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val, in LowerSTOREVector()
2600 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, LoadVT, P, in LowerFormalArguments()
4886 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, SubVector, in ReplaceLoadVector()
[all …]
/external/llvm-project/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp373 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom); in NVPTXTargetLowering()
1884 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp, in LowerCONCAT_VECTORS()
1932 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector, in LowerEXTRACT_VECTOR_ELT()
1934 SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector, in LowerEXTRACT_VECTOR_ELT()
2170 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
2358 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val, in LowerSTOREVector()
2360 SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val, in LowerSTOREVector()
2368 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val, in LowerSTOREVector()
2582 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, LoadVT, P, in LowerFormalArguments()
4865 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, SubVector, in ReplaceLoadVector()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp353 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal); in SystemZTargetLowering()
493 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); in SystemZTargetLowering()
494 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); in SystemZTargetLowering()
638 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in SystemZTargetLowering()
1315 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VA.getLocVT(), Value, in convertValVTToLocVT()
4701 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in tryBuildVectorShuffle()
5011 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT, in lowerEXTRACT_VECTOR_ELT()
5195 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
5543 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op, in combineExtract()
5556 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineTruncateExtract()
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