| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64PostLegalizerCombiner.cpp | 101 auto Elt0 = B.buildExtractVectorElement(Ty, Src, B.buildConstant(s64, 0)); in applyExtractVecEltPairwiseAdd() local
103 B.buildInstr(Opc, {MI.getOperand(0).getReg()}, {Elt0, Elt1}); in applyExtractVecEltPairwiseAdd()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/IR/ |
| D | AutoUpgrade.cpp | 1815 Value *Elt0 = Builder.CreateExtractElement(Vec, (uint64_t)0); in UpgradeIntrinsicCall() local
1817 Intrinsic::sqrt, Elt0->getType()); in UpgradeIntrinsicCall()
1818 Elt0 = Builder.CreateCall(Intr, Elt0); in UpgradeIntrinsicCall()
1819 Rep = Builder.CreateInsertElement(Vec, Elt0, (uint64_t)0); in UpgradeIntrinsicCall()
1931 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), in UpgradeIntrinsicCall() local
1937 EltOp = Builder.CreateFAdd(Elt0, Elt1); in UpgradeIntrinsicCall()
1939 EltOp = Builder.CreateFSub(Elt0, Elt1); in UpgradeIntrinsicCall()
1941 EltOp = Builder.CreateFMul(Elt0, Elt1); in UpgradeIntrinsicCall()
1943 EltOp = Builder.CreateFDiv(Elt0, Elt1); in UpgradeIntrinsicCall()
|
| /external/llvm-project/llvm/lib/IR/ |
| D | AutoUpgrade.cpp | 1924 Value *Elt0 = Builder.CreateExtractElement(Vec, (uint64_t)0); in UpgradeIntrinsicCall() local
1926 Intrinsic::sqrt, Elt0->getType()); in UpgradeIntrinsicCall()
1927 Elt0 = Builder.CreateCall(Intr, Elt0); in UpgradeIntrinsicCall()
1928 Rep = Builder.CreateInsertElement(Vec, Elt0, (uint64_t)0); in UpgradeIntrinsicCall()
2040 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), in UpgradeIntrinsicCall() local
2046 EltOp = Builder.CreateFAdd(Elt0, Elt1); in UpgradeIntrinsicCall()
2048 EltOp = Builder.CreateFSub(Elt0, Elt1); in UpgradeIntrinsicCall()
2050 EltOp = Builder.CreateFMul(Elt0, Elt1); in UpgradeIntrinsicCall()
2052 EltOp = Builder.CreateFDiv(Elt0, Elt1); in UpgradeIntrinsicCall()
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 1184 SDValue Elt0 = OutVals[OIdx++]; in LowerCall() local
1187 Elt0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt0); in LowerCall()
1194 DAG.getConstant(0, dl, MVT::i32), Elt0, in LowerCall()
2243 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P, in LowerFormalArguments() local
2249 Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0); in LowerFormalArguments()
2253 InVals.push_back(Elt0); in LowerFormalArguments()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 3208 SDValue Elt0 = Vec.getOperand(0); in performTruncateCombine() local
3209 EVT EltVT = Elt0.getValueType(); in performTruncateCombine()
3212 Elt0 = DAG.getNode(ISD::BITCAST, SL, in performTruncateCombine()
3213 EltVT.changeTypeToInteger(), Elt0); in performTruncateCombine()
3216 return DAG.getNode(ISD::TRUNCATE, SL, VT, Elt0); in performTruncateCombine()
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| D | SIISelLowering.cpp | 4965 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, in lowerVECTOR_SHUFFLE() local
4971 Pieces.push_back(DAG.getBuildVector(PackVT, SL, { Elt0, Elt1 })); in lowerVECTOR_SHUFFLE()
9323 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, in performExtractVectorEltCombine() local
9328 DCI.AddToWorklist(Elt0.getNode()); in performExtractVectorEltCombine()
9330 return DAG.getNode(Opc, SL, EltVT, Elt0, Elt1, Vec->getFlags()); in performExtractVectorEltCombine()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 3214 SDValue Elt0 = Vec.getOperand(0); in performTruncateCombine() local
3215 EVT EltVT = Elt0.getValueType(); in performTruncateCombine()
3218 Elt0 = DAG.getNode(ISD::BITCAST, SL, in performTruncateCombine()
3219 EltVT.changeTypeToInteger(), Elt0); in performTruncateCombine()
3222 return DAG.getNode(ISD::TRUNCATE, SL, VT, Elt0); in performTruncateCombine()
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| D | SIISelLowering.cpp | 5552 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, in lowerVECTOR_SHUFFLE() local
5558 Pieces.push_back(DAG.getBuildVector(PackVT, SL, { Elt0, Elt1 })); in lowerVECTOR_SHUFFLE()
7368 SDValue Elt0 = Ops.pop_back_val(); in LowerINTRINSIC_W_CHAIN() local
7372 { Elt0, Lanes[0] }))); in LowerINTRINSIC_W_CHAIN()
10089 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, in performExtractVectorEltCombine() local
10094 DCI.AddToWorklist(Elt0.getNode()); in performExtractVectorEltCombine()
10096 return DAG.getNode(Opc, SL, EltVT, Elt0, Elt1, Vec->getFlags()); in performExtractVectorEltCombine()
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| /external/llvm/test/CodeGen/X86/ |
| D | masked_gather_scatter.ll | 184 ; SCALAR-NEXT: %Elt0 = extractelement <16 x i32> %val, i32 0
186 ; SCALAR-NEXT: store i32 %Elt0, i32* %Ptr0, align 4
234 ; SCALAR: store i32 %Elt0, i32* %Ptr01, align 4
|
| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | masked_gather_scatter.ll | 220 ; SCALAR-NEXT: %Elt0 = extractelement <16 x i32> %val, i64 0
222 ; SCALAR-NEXT: store i32 %Elt0, i32* %Ptr0, align 4
283 ; SCALAR: store i32 %Elt0, i32* %Ptr01, align 4
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 8137 size_t Elt0 = *FirstRealEltIter - FirstRealIndex; in isWideDUPMask() local
8140 if (Elt0 % NumEltsPerBlock != 0) in isWideDUPMask()
8145 if (BlockElts[I] >= 0 && (unsigned)BlockElts[I] != Elt0 + I) in isWideDUPMask()
8148 DupLaneOp = Elt0 / NumEltsPerBlock; in isWideDUPMask()
|