| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonConstExtenders.cpp | 389 bool isRegOffOpcode(unsigned ExtOpc) const ;
390 unsigned getRegOffOpcode(unsigned ExtOpc) const;
391 unsigned getDirectRegReplacement(unsigned ExtOpc) const;
864 unsigned HCE::getRegOffOpcode(unsigned ExtOpc) const { in getRegOffOpcode()
868 switch (ExtOpc) { in getRegOffOpcode()
873 const MCInstrDesc &D = HII->get(ExtOpc); in getRegOffOpcode()
881 switch (ExtOpc) { in getRegOffOpcode()
954 if (!isStoreImmediate(ExtOpc)) in getRegOffOpcode()
955 return ExtOpc; in getRegOffOpcode()
964 unsigned HCE::getDirectRegReplacement(unsigned ExtOpc) const { in getDirectRegReplacement()
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| D | HexagonBitSimplify.cpp | 2517 unsigned ExtOpc = 0; in simplifyExtractLow() local
2520 ExtOpc = Signed ? Hexagon::A2_sxtb : Hexagon::A2_zxtb; in simplifyExtractLow()
2522 ExtOpc = Signed ? Hexagon::A2_sxth : Hexagon::A2_zxth; in simplifyExtractLow()
2524 ExtOpc = Hexagon::A2_andir; in simplifyExtractLow()
2526 if (ExtOpc == 0) { in simplifyExtractLow()
2527 ExtOpc = in simplifyExtractLow()
2539 if (!validateReg({R,SR}, ExtOpc, 1)) in simplifyExtractLow()
2543 if (MI->getOpcode() == ExtOpc) { in simplifyExtractLow()
2555 auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR) in simplifyExtractLow()
2557 switch (ExtOpc) { in simplifyExtractLow()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonConstExtenders.cpp | 390 bool isRegOffOpcode(unsigned ExtOpc) const ;
391 unsigned getRegOffOpcode(unsigned ExtOpc) const;
392 unsigned getDirectRegReplacement(unsigned ExtOpc) const;
865 unsigned HCE::getRegOffOpcode(unsigned ExtOpc) const { in getRegOffOpcode()
869 switch (ExtOpc) { in getRegOffOpcode()
874 const MCInstrDesc &D = HII->get(ExtOpc); in getRegOffOpcode()
882 switch (ExtOpc) { in getRegOffOpcode()
955 if (!isStoreImmediate(ExtOpc)) in getRegOffOpcode()
956 return ExtOpc; in getRegOffOpcode()
965 unsigned HCE::getDirectRegReplacement(unsigned ExtOpc) const { in getDirectRegReplacement()
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| D | HexagonBitSimplify.cpp | 2507 unsigned ExtOpc = 0; in simplifyExtractLow() local
2510 ExtOpc = Signed ? Hexagon::A2_sxtb : Hexagon::A2_zxtb; in simplifyExtractLow()
2512 ExtOpc = Signed ? Hexagon::A2_sxth : Hexagon::A2_zxth; in simplifyExtractLow()
2514 ExtOpc = Hexagon::A2_andir; in simplifyExtractLow()
2516 if (ExtOpc == 0) { in simplifyExtractLow()
2517 ExtOpc = in simplifyExtractLow()
2529 if (!validateReg({R,SR}, ExtOpc, 1)) in simplifyExtractLow()
2533 if (MI->getOpcode() == ExtOpc) { in simplifyExtractLow()
2545 auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR) in simplifyExtractLow()
2547 switch (ExtOpc) { in simplifyExtractLow()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 443 MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc, in buildExtOrTrunc() argument
446 assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc || in buildExtOrTrunc()
447 TargetOpcode::G_SEXT == ExtOpc) && in buildExtOrTrunc()
457 Opcode = ExtOpc; in buildExtOrTrunc()
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| D | LegalizerHelper.cpp | 1700 unsigned ExtOpc = LI.getExtOpcodeForWideningConstant( in widenScalar() local
1702 assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT || in widenScalar()
1703 ExtOpc == TargetOpcode::G_ANYEXT) && in widenScalar()
1706 const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT) in widenScalar()
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 438 MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc, in buildExtOrTrunc() argument
441 assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc || in buildExtOrTrunc()
442 TargetOpcode::G_SEXT == ExtOpc) && in buildExtOrTrunc()
452 Opcode = ExtOpc; in buildExtOrTrunc()
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| D | LegalizerHelper.cpp | 2083 unsigned ExtOpc = LI.getExtOpcodeForWideningConstant( in widenScalar() local
2085 assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT || in widenScalar()
2086 ExtOpc == TargetOpcode::G_ANYEXT) && in widenScalar()
2089 const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT) in widenScalar()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 610 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterBankInfo.cpp | 1914 unsigned ExtOpc, in extendLow32IntoHigh32() argument
1917 if (ExtOpc == AMDGPU::G_ZEXT) { in extendLow32IntoHigh32()
1919 } else if (ExtOpc == AMDGPU::G_SEXT) { in extendLow32IntoHigh32()
1931 assert(ExtOpc == AMDGPU::G_ANYEXT && "not an integer extension"); in extendLow32IntoHigh32()
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| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 707 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1266 unsigned ExtOpc = ISD::isSignedIntSetCC(CC) ? ISD::SIGN_EXTEND in LowerSETCC() local
1268 SDValue LX = DAG.getNode(ExtOpc, dl, MVT::v2i32, LHS); in LowerSETCC()
1269 SDValue RX = DAG.getNode(ExtOpc, dl, MVT::v2i32, RHS); in LowerSETCC()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 1134 unsigned ExtOpc = in PromoteOperand() local
1136 return DAG.getNode(ExtOpc, DL, PVT, Op); in PromoteOperand()
9163 unsigned ExtOpc, in ExtendUsesToFormExtLoad() argument
9177 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { in ExtendUsesToFormExtLoad()
9179 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) in ExtendUsesToFormExtLoad()
9502 ISD::NodeType ExtOpc) { in tryToFoldExtOfLoad() argument
9513 DoXform = ExtendUsesToFormExtLoad(VT, N, N0, ExtOpc, SetCCs, TLI); in tryToFoldExtOfLoad()
9523 Combiner.ExtendSetCCUses(SetCCs, N0, ExtLoad, ExtOpc); in tryToFoldExtOfLoad()
9542 ISD::NodeType ExtOpc) { in tryToFoldExtOfMaskedLoad() argument
9557 SDValue PassThru = DAG.getNode(ExtOpc, dl, VT, Ld->getPassThru()); in tryToFoldExtOfMaskedLoad()
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| D | TargetLowering.cpp | 4147 ISD::NodeType ExtOpc = IsBool ? getExtendForContent(BCont) in LowerAsmOperandForConstraint() local
4149 int64_t ExtVal = ExtOpc == ISD::ZERO_EXTEND ? C->getZExtValue() in LowerAsmOperandForConstraint()
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 1243 unsigned ExtOpc = in PromoteOperand() local
1245 return DAG.getNode(ExtOpc, DL, PVT, Op); in PromoteOperand()
10060 unsigned ExtOpc, in ExtendUsesToFormExtLoad() argument
10074 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { in ExtendUsesToFormExtLoad()
10076 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) in ExtendUsesToFormExtLoad()
10398 ISD::NodeType ExtOpc) { in tryToFoldExtOfLoad() argument
10409 DoXform = ExtendUsesToFormExtLoad(VT, N, N0, ExtOpc, SetCCs, TLI); in tryToFoldExtOfLoad()
10419 Combiner.ExtendSetCCUses(SetCCs, N0, ExtLoad, ExtOpc); in tryToFoldExtOfLoad()
10438 ISD::NodeType ExtOpc) { in tryToFoldExtOfMaskedLoad() argument
10453 SDValue PassThru = DAG.getNode(ExtOpc, dl, VT, Ld->getPassThru()); in tryToFoldExtOfMaskedLoad()
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| D | TargetLowering.cpp | 4442 ISD::NodeType ExtOpc = IsBool ? getExtendForContent(BCont) in LowerAsmOperandForConstraint() local
4444 int64_t ExtVal = ExtOpc == ISD::ZERO_EXTEND ? C->getZExtValue() in LowerAsmOperandForConstraint()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 20610 static SDValue SplitAndExtendv16i1(unsigned ExtOpc, MVT VT, SDValue In, in SplitAndExtendv16i1() argument
20617 Lo = DAG.getNode(ExtOpc, dl, MVT::v8i16, Lo); in SplitAndExtendv16i1()
20618 Hi = DAG.getNode(ExtOpc, dl, MVT::v8i16, Hi); in SplitAndExtendv16i1()
23713 unsigned ExtOpc = in LowerEXTEND_VECTOR_INREG() local
23716 return DAG.getNode(ExtOpc, dl, VT, In); in LowerEXTEND_VECTOR_INREG()
27936 unsigned ExtOpc = Opc == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerShift() local
27937 R = DAG.getNode(ExtOpc, dl, ExtVT, R); in LowerShift()
42412 unsigned ExtOpc = LHS.getOpcode(); in combineShiftToPMULH() local
42413 if ((ExtOpc != ISD::SIGN_EXTEND && ExtOpc != ISD::ZERO_EXTEND) || in combineShiftToPMULH()
42414 RHS.getOpcode() != ExtOpc) in combineShiftToPMULH()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 982 unsigned ExtOpc = in PromoteOperand() local
984 return DAG.getNode(ExtOpc, dl, PVT, Op); in PromoteOperand()
5838 unsigned ExtOpc, in ExtendUsesToFormExtLoad() argument
5852 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { in ExtendUsesToFormExtLoad()
5854 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) in ExtendUsesToFormExtLoad()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 19637 static SDValue SplitAndExtendv16i1(unsigned ExtOpc, MVT VT, SDValue In, in SplitAndExtendv16i1() argument
19644 Lo = DAG.getNode(ExtOpc, dl, MVT::v8i16, Lo); in SplitAndExtendv16i1()
19645 Hi = DAG.getNode(ExtOpc, dl, MVT::v8i16, Hi); in SplitAndExtendv16i1()
22484 unsigned ExtOpc = in LowerEXTEND_VECTOR_INREG() local
22487 return DAG.getNode(ExtOpc, dl, VT, In); in LowerEXTEND_VECTOR_INREG()
26849 unsigned ExtOpc = Opc == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerShift() local
26850 R = DAG.getNode(ExtOpc, dl, ExtVT, R); in LowerShift()
42218 unsigned ExtOpc = LHS.getOpcode(); in combinePMULH() local
42219 if ((ExtOpc != ISD::SIGN_EXTEND && ExtOpc != ISD::ZERO_EXTEND) || in combinePMULH()
42220 RHS.getOpcode() != ExtOpc) in combinePMULH()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 20340 unsigned ExtOpc = in LowerShift() local
20342 R = DAG.getNode(ExtOpc, dl, ExtVT, R); in LowerShift()
|