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Searched refs:ExtReg (Results 1 – 20 of 20) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsCallLowering.cpp281 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
282 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
317 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
318 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
326 Register ExtReg = MRI.createGenericVirtualRegister(LocTy); in extendRegister() local
327 MIRBuilder.buildSExt(ExtReg, ValReg); in extendRegister()
328 return ExtReg; in extendRegister()
331 Register ExtReg = MRI.createGenericVirtualRegister(LocTy); in extendRegister() local
332 MIRBuilder.buildZExt(ExtReg, ValReg); in extendRegister()
333 return ExtReg; in extendRegister()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallLowering.cpp128 Register ExtReg; in assignValueToReg() local
142 ExtReg = MIB->getOperand(0).getReg(); in assignValueToReg()
144 ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
146 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
151 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
155 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
/external/llvm-project/llvm/lib/Target/X86/
DX86CallLowering.cpp125 Register ExtReg; in assignValueToReg() local
139 ExtReg = in assignValueToReg()
142 ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
144 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
150 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
155 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
DX86FastISel.cpp1095 Register ExtReg = createResultReg(&X86::GR64RegClass); in X86SelectCallAddress() local
1097 TII.get(TargetOpcode::SUBREG_TO_REG), ExtReg) in X86SelectCallAddress()
1101 Reg = ExtReg; in X86SelectCallAddress()
/external/llvm-project/llvm/lib/Target/ARM/
DARMCallLowering.cpp119 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
120 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
129 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
133 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallLowering.cpp123 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
124 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
133 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
137 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUCallLowering.cpp74 Register ExtReg = extendRegisterMin32(ValVReg, VA); in assignValueToReg() local
83 {MRI.getType(ExtReg)}, false) in assignValueToReg()
84 .addReg(ExtReg); in assignValueToReg()
85 ExtReg = ToSGPR.getReg(0); in assignValueToReg()
88 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
234 Register ExtReg = extendRegisterMin32(ValVReg, VA); in assignValueToReg() local
235 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
DAMDGPUInstructionSelector.cpp2050 Register ExtReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass); in selectG_SZA_EXT() local
2055 BuildMI(MBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), ExtReg) in selectG_SZA_EXT()
2062 .addReg(ExtReg) in selectG_SZA_EXT()
/external/llvm-project/llvm/lib/Target/Mips/
DMipsCallLowering.cpp252 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
253 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
286 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
287 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUCallLowering.cpp54 Register ExtReg; in assignValueToReg() local
58 ExtReg = MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0); in assignValueToReg()
60 ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
62 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
DAMDGPUInstructionSelector.cpp1383 Register ExtReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass); in selectG_SZA_EXT() local
1386 BuildMI(MBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), ExtReg) in selectG_SZA_EXT()
1393 .addReg(ExtReg) in selectG_SZA_EXT()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstructionSelector.cpp259 Register narrowExtendRegIfNeeded(Register ExtReg,
4539 Register ExtReg = in selectAddrModeWRO() local
4545 [=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }, in selectAddrModeWRO()
4771 Register ExtReg, MachineIRBuilder &MIB) const { in narrowExtendRegIfNeeded() argument
4773 if (MRI.getType(ExtReg).getSizeInBits() == 32) in narrowExtendRegIfNeeded()
4774 return ExtReg; in narrowExtendRegIfNeeded()
4778 auto Copy = MIB.buildCopy({NarrowReg}, {ExtReg}); in narrowExtendRegIfNeeded()
4796 Register ExtReg; in selectArithExtendedRegister() local
4823 ExtReg = ExtDef->getOperand(1).getReg(); in selectArithExtendedRegister()
4829 ExtReg = RootDef->getOperand(1).getReg(); in selectArithExtendedRegister()
[all …]
DAArch64CallLowering.cpp172 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
173 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp884 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass); in PPCEmitCmp() local
885 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
887 SrcReg1 = ExtReg; in PPCEmitCmp()
890 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass); in PPCEmitCmp() local
891 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
893 SrcReg2 = ExtReg; in PPCEmitCmp()
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp936 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass); in PPCEmitCmp() local
937 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
939 SrcReg1 = ExtReg; in PPCEmitCmp()
942 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass); in PPCEmitCmp() local
943 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
945 SrcReg2 = ExtReg; in PPCEmitCmp()
DPPCISelLowering.cpp11300 Register ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); in EmitAtomicBinary() local
11302 ExtReg).addReg(dest); in EmitAtomicBinary()
11304 .addReg(incr).addReg(ExtReg); in EmitAtomicBinary()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp934 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass); in PPCEmitCmp() local
935 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
937 SrcReg1 = ExtReg; in PPCEmitCmp()
940 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass); in PPCEmitCmp() local
941 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
943 SrcReg2 = ExtReg; in PPCEmitCmp()
DPPCISelLowering.cpp10708 Register ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); in EmitAtomicBinary() local
10710 ExtReg).addReg(dest); in EmitAtomicBinary()
10712 .addReg(incr).addReg(ExtReg); in EmitAtomicBinary()
/external/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64CallLowering.cpp169 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
170 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
DAArch64InstructionSelector.cpp5460 Register ExtReg = moveScalarRegClass(OffsetInst->getOperand(1).getReg(), in selectAddrModeWRO() local
5466 [=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }, in selectAddrModeWRO()
5761 Register ExtReg; in selectArithExtendedRegister() local
5788 ExtReg = ExtDef->getOperand(1).getReg(); in selectArithExtendedRegister()
5794 ExtReg = RootDef->getOperand(1).getReg(); in selectArithExtendedRegister()
5800 if (Ext == AArch64_AM::UXTW && MRI.getType(ExtReg).getSizeInBits() == 32) { in selectArithExtendedRegister()
5801 MachineInstr *ExtInst = MRI.getVRegDef(ExtReg); in selectArithExtendedRegister()
5810 ExtReg = moveScalarRegClass(ExtReg, AArch64::GPR32RegClass, MIB); in selectArithExtendedRegister()
5812 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }, in selectArithExtendedRegister()