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Searched refs:ExtType (Results 1 – 25 of 109) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
DHexagonBitTracker.h50 struct ExtType { struct
54 ExtType() : Type(0), Width(0) {} in ExtType() function
55 ExtType(char t, uint16_t w) : Type(t), Width(w) {} in ExtType() function
58 typedef DenseMap<unsigned, ExtType> RegExtMap;
DHexagonISelDAGToDAG.cpp250 ISD::LoadExtType ExtType = LD->getExtensionType(); in SelectIndexedLoad() local
251 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD); in SelectIndexedLoad()
304 auto getExt64 = [this,ExtType] (MachineSDNode *N, const SDLoc &dl) in SelectIndexedLoad()
306 if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) { in SelectIndexedLoad()
311 if (ExtType == ISD::SEXTLOAD) in SelectIndexedLoad()
322 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) { in SelectIndexedLoad()
DHexagonBitTracker.cpp71 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::SExt, Width))); in HexagonEvaluator()
73 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::ZExt, Width))); in HexagonEvaluator()
1120 if (F->second.Type == ExtType::SExt) in evaluateFormalCopy()
1122 else if (F->second.Type == ExtType::ZExt) in evaluateFormalCopy()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonBitTracker.h61 struct ExtType { struct
64 ExtType() = default;
65 ExtType(char t, uint16_t w) : Type(t), Width(w) {} in ExtType() function
71 using RegExtMap = DenseMap<unsigned, ExtType>;
DHexagonBitTracker.cpp83 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::SExt, Width))); in HexagonEvaluator()
85 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::ZExt, Width))); in HexagonEvaluator()
1238 if (F->second.Type == ExtType::SExt) in evaluateFormalCopy()
1240 else if (F->second.Type == ExtType::ZExt) in evaluateFormalCopy()
DHexagonISelDAGToDAG.cpp77 ISD::LoadExtType ExtType = LD->getExtensionType(); in SelectIndexedLoad() local
78 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD); in SelectIndexedLoad()
132 auto getExt64 = [this,ExtType] (MachineSDNode *N, const SDLoc &dl) in SelectIndexedLoad()
134 if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) { in SelectIndexedLoad()
139 if (ExtType == ISD::SEXTLOAD) in SelectIndexedLoad()
150 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) { in SelectIndexedLoad()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonBitTracker.h61 struct ExtType { struct
64 ExtType() = default;
65 ExtType(char t, uint16_t w) : Type(t), Width(w) {} in ExtType() argument
71 using RegExtMap = DenseMap<unsigned, ExtType>;
DHexagonBitTracker.cpp83 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::SExt, Width))); in HexagonEvaluator()
85 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::ZExt, Width))); in HexagonEvaluator()
1236 if (F->second.Type == ExtType::SExt) in evaluateFormalCopy()
1238 else if (F->second.Type == ExtType::ZExt) in evaluateFormalCopy()
DHexagonISelDAGToDAG.cpp77 ISD::LoadExtType ExtType = LD->getExtensionType(); in SelectIndexedLoad() local
78 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD); in SelectIndexedLoad()
132 auto getExt64 = [this,ExtType] (MachineSDNode *N, const SDLoc &dl) in SelectIndexedLoad()
134 if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) { in SelectIndexedLoad()
139 if (ExtType == ISD::SEXTLOAD) in SelectIndexedLoad()
150 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) { in SelectIndexedLoad()
/external/llvm/include/llvm/Target/
DTargetLowering.h657 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, in getLoadExtAction() argument
662 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE && in getLoadExtAction()
664 unsigned Shift = 4 * ExtType; in getLoadExtAction()
669 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const { in isLoadExtLegal() argument
670 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal; in isLoadExtLegal()
675 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const { in isLoadExtLegalOrCustom() argument
676 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal || in isLoadExtLegalOrCustom()
677 getLoadExtAction(ExtType, ValVT, MemVT) == Custom; in isLoadExtLegalOrCustom()
1433 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, in setLoadExtAction() argument
1435 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() && in setLoadExtAction()
[all …]
/external/llvm-project/clang/lib/CodeGen/
DCGOpenCLRuntime.cpp64 #define EXT_OPAQUE_TYPE(ExtType, Id, Ext) \ in convertOpenCLSpecificType() argument
67 llvm::StructType::create(Ctx, "opencl." #ExtType), AddrSpc); in convertOpenCLSpecificType()
/external/llvm-project/llvm/include/llvm/CodeGen/
DSelectionDAG.h1239 getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain,
1246 getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain,
1251 return getExtLoad(ExtType, dl, VT, Chain, Ptr, PtrInfo, MemVT,
1254 SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT,
1259 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
1266 ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl,
1272 return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, PtrInfo, MemVT,
1278 getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
1284 return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, PtrInfo, MemVT,
1287 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
DTargetLowering.h1216 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, in getLoadExtAction() argument
1221 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE && in getLoadExtAction()
1223 unsigned Shift = 4 * ExtType; in getLoadExtAction()
1228 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const { in isLoadExtLegal() argument
1229 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal; in isLoadExtLegal()
1234 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const { in isLoadExtLegalOrCustom() argument
1235 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal || in isLoadExtLegalOrCustom()
1236 getLoadExtAction(ExtType, ValVT, MemVT) == Custom; in isLoadExtLegalOrCustom()
2160 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, in setLoadExtAction() argument
2162 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() && in setLoadExtAction()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DTargetLowering.h1064 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, in getLoadExtAction() argument
1069 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE && in getLoadExtAction()
1071 unsigned Shift = 4 * ExtType; in getLoadExtAction()
1076 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const { in isLoadExtLegal() argument
1077 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal; in isLoadExtLegal()
1082 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const { in isLoadExtLegalOrCustom() argument
1083 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal || in isLoadExtLegalOrCustom()
1084 getLoadExtAction(ExtType, ValVT, MemVT) == Custom; in isLoadExtLegalOrCustom()
2011 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, in setLoadExtAction() argument
2013 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() && in setLoadExtAction()
[all …]
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp1098 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val); in printArithExtend() local
1104 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { in printArithExtend()
1108 ExtType == AArch64_AM::UXTX) || in printArithExtend()
1110 ExtType == AArch64_AM::UXTW) ) { in printArithExtend()
1116 O << ", " << AArch64_AM::getShiftExtendName(ExtType); in printArithExtend()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DCombinerHelper.cpp951 LLT ExtType = Ty.getScalarType(); in getMemsetValue() local
952 auto ZExt = MIB.buildZExtOrTrunc(ExtType, Val); in getMemsetValue()
955 auto MagicMI = MIB.buildConstant(ExtType, Magic); in getMemsetValue()
956 Val = MIB.buildMul(ExtType, ZExt, MagicMI).getReg(0); in getMemsetValue()
959 assert(ExtType == Ty && "Vector memset value type not supported yet"); in getMemsetValue()
/external/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64InstPrinter.cpp1008 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val); in printArithExtend() local
1014 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { in printArithExtend()
1018 ExtType == AArch64_AM::UXTX) || in printArithExtend()
1020 ExtType == AArch64_AM::UXTW) ) { in printArithExtend()
1026 O << ", " << AArch64_AM::getShiftExtendName(ExtType); in printArithExtend()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64InstPrinter.cpp994 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val); in printArithExtend() local
1000 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { in printArithExtend()
1004 ExtType == AArch64_AM::UXTX) || in printArithExtend()
1006 ExtType == AArch64_AM::UXTW) ) { in printArithExtend()
1012 O << ", " << AArch64_AM::getShiftExtendName(ExtType); in printArithExtend()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp204 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeOp() local
205 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) in LegalizeOp()
513 ISD::LoadExtType ExtType = LD->getExtensionType(); in ExpandLoad() local
602 switch (ExtType) { in ExpandLoad()
DLegalizeVectorTypes.cpp1049 ISD::LoadExtType ExtType = LD->getExtensionType(); in SplitVecRes_LOAD() local
1063 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
1070 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
1096 ISD::LoadExtType ExtType = MLD->getExtensionType(); in SplitVecRes_MLOAD() local
1127 ExtType); in SplitVecRes_MLOAD()
1139 ExtType); in SplitVecRes_MLOAD()
2839 ISD::LoadExtType ExtType = LD->getExtensionType(); in WidenVecRes_LOAD() local
2843 if (ExtType != ISD::NON_EXTLOAD) in WidenVecRes_LOAD()
2844 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType); in WidenVecRes_LOAD()
2870 ISD::LoadExtType ExtType = N->getExtensionType(); in WidenVecRes_MLOAD() local
[all …]
DLegalizeDAG.cpp625 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeLoadOps() local
626 if (ExtType == ISD::NON_EXTLOAD) { in LegalizeLoadOps()
693 TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) == in LegalizeLoadOps()
705 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeLoadOps()
715 if (ExtType == ISD::SEXTLOAD) in LegalizeLoadOps()
720 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) in LegalizeLoadOps()
756 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr, in LegalizeLoadOps()
778 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr, in LegalizeLoadOps()
811 switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0), in LegalizeLoadOps()
846 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) { in LegalizeLoadOps()
[all …]
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp1613 ISD::LoadExtType ExtType = LD->getExtensionType(); in SplitVecRes_LOAD() local
1632 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
1639 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, MPI, in SplitVecRes_LOAD()
1666 ISD::LoadExtType ExtType = MLD->getExtensionType(); in SplitVecRes_MLOAD() local
1697 MMO, MLD->getAddressingMode(), ExtType, in SplitVecRes_MLOAD()
1722 HiMemVT, MMO, MLD->getAddressingMode(), ExtType, in SplitVecRes_MLOAD()
1751 ISD::LoadExtType ExtType = MGT->getExtensionType(); in SplitVecRes_MGATHER() local
1787 MMO, MGT->getIndexType(), ExtType); in SplitVecRes_MGATHER()
1791 MMO, MGT->getIndexType(), ExtType); in SplitVecRes_MGATHER()
2396 ISD::LoadExtType ExtType = MGT->getExtensionType(); in SplitVecOp_MGATHER() local
[all …]
/external/capstone/arch/AArch64/
DAArch64InstPrinter.c1027 AArch64_AM_ShiftExtendType ExtType = AArch64_AM_getArithExtendType(Val); in printArithExtend() local
1033 if (ExtType == AArch64_AM_UXTW || ExtType == AArch64_AM_UXTX) { in printArithExtend()
1037 ExtType == AArch64_AM_UXTX) || in printArithExtend()
1039 ExtType == AArch64_AM_UXTW) ) { in printArithExtend()
1053 SStream_concat(O, ", %s", AArch64_AM_getShiftExtendName(ExtType)); in printArithExtend()
1056 switch(ExtType) { in printArithExtend()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.h140 ISD::LoadExtType ExtType,
/external/llvm-project/clang/lib/Serialization/
DASTCommon.cpp215 #define EXT_OPAQUE_TYPE(ExtType, Id, Ext) \ in TypeIdxFromBuiltin() argument

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