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Searched refs:FADD_S (Results 1 – 25 of 25) sorted by relevance

/external/mesa3d/src/mesa/x86/
Dx86_xform2.S127 FADD_S( MAT12 )
129 FADD_S( MAT13 )
131 FADD_S( MAT14 )
133 FADD_S( MAT15 )
278 FADD_S( MAT12 )
280 FADD_S( MAT13 )
282 FADD_S( MAT14 )
350 FADD_S( MAT12 )
425 FADD_S( MAT12 )
427 FADD_S( MAT13 )
[all …]
Dx86_xform3.S143 FADD_S( MAT12 )
145 FADD_S( MAT13 )
147 FADD_S( MAT14 )
149 FADD_S( MAT15 )
321 FADD_S( MAT12 )
323 FADD_S( MAT13 )
325 FADD_S( MAT14 )
394 FADD_S( MAT12 )
472 FADD_S( MAT12 )
474 FADD_S( MAT13 )
[all …]
Dassyntax.h690 #define FADD_S(a) CHOICE(fadds a, fadds a, fadds a) macro
1403 #define FADD_S(a) fadd S_(a) macro
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
Dfloat_arithmetic_operations.mir30 ; FP32: [[FADD_S:%[0-9]+]]:fgr32 = FADD_S [[COPY]], [[COPY1]]
31 ; FP32: $f0 = COPY [[FADD_S]]
37 ; FP64: [[FADD_S:%[0-9]+]]:fgr32 = FADD_S [[COPY]], [[COPY1]]
38 ; FP64: $f0 = COPY [[FADD_S]]
/external/llvm-project/llvm/test/DebugInfo/MIR/Mips/
Dlive-debug-values-reg-copy.mir212 renamable $f0 = FADD_S killed renamable $f0, killed renamable $f1, debug-location !19
225 renamable $f24 = FADD_S killed renamable $f12, killed renamable $f0, debug-location !19
236 renamable $f0 = FADD_S killed renamable $f25, killed renamable $f0, debug-location !19
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoF.td133 def FADD_S : FPALUS_rr_frm<0b0000000, "fadd.s">,
135 def : FPALUSDynFrmAlias<FADD_S, "fadd.s">;
305 def : PatFpr32Fpr32DynFrm<fadd, FADD_S>;
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoF.td132 def FADD_S : FPALUS_rr_frm<0b0000000, "fadd.s">,
134 def : FPALUSDynFrmAlias<FADD_S, "fadd.s">;
311 def : PatFpr32Fpr32DynFrm<fadd, FADD_S>;
/external/llvm/lib/Target/Mips/
DMipsInstrFPU.td468 def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsScheduleP5600.td451 (instrs FADD_D32, FADD_D64, FADD_S, FMUL_D32, FMUL_D64, FMUL_S,
DMipsInstrFPU.td633 def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
DMipsScheduleGeneric.td811 FADD_D64, FADD_S, MADD_S, MSUB_S, FMUL_S,
/external/llvm-project/llvm/lib/Target/Mips/
DMipsScheduleP5600.td452 (instrs FADD_D32, FADD_D64, FADD_PS64, FADD_S, FMUL_D32, FMUL_D64,
DMipsInstrFPU.td666 def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
DMipsScheduleGeneric.td811 FADD_D64, FADD_S, MADD_S, MSUB_S, FMUL_S,
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc884 {DBGFIELD("FADD_S") 1, false, false, 14, 2, 4, 1, 0, 0}, // #624
2568 {DBGFIELD("FADD_S") 1, false, false, 57, 2, 4, 1, 0, 0}, // #624
DMipsGenMCCodeEmitter.inc1480 UINT64_C(1174405120), // FADD_S
3511 case Mips::FADD_S:
10942 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FADD_S = 1467
DMipsGenAsmWriter.inc2708 268458825U, // FADD_S
5462 0U, // FADD_S
DMipsGenInstrInfo.inc1482 FADD_S = 1467,
3404 FADD_S = 624,
6328 …MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1467 = FADD_S
16786 { Mips::FADD_S, Mips::FADD_S, Mips::FADD_S_MM },
DMipsGenFastISel.inc1457 return fastEmitInst_rr(Mips::FADD_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
DMipsGenDisassemblerTables.inc3360 /* 2622 */ MCD::OPC_Decode, 187, 11, 207, 1, // Opcode: FADD_S
DMipsGenAsmMatcher.inc5457 …{ 55 /* add.s */, Mips::FADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_Has…
DMipsGenGlobalISel.inc21571 …// (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S:{ *:[f32] …
21572 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_S,
DMipsGenDAGISel.inc27348 /* 51727*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FADD_S), 0,
27351 … // Dst: (FADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc703 134240572U, // FADD_S
2492 0U, // FADD_S
DMipsGenDisassemblerTables.inc1040 /* 1805 */ MCD_OPC_Decode, 174, 5, 93, // Opcode: FADD_S