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Searched refs:FCANONICALIZE (Results 1 – 25 of 34) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-fcanonicalize.mir47 ; SI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[FPEXT]]
48 ; SI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCANONICALIZE]](s32)
54 ; VI: [[FCANONICALIZE:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC]]
55 ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCANONICALIZE]](s16)
60 ; GFX9: [[FCANONICALIZE:%[0-9]+]]:_(s16) = G_FCANONICALIZE [[TRUNC]]
61 ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCANONICALIZE]](s16)
79 ; SI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV]]
81 …; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FCANONICALIZE]](s32), [[FCANONICALI…
86 ; VI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[UV]]
88 …; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FCANONICALIZE]](s32), [[FCANONICALI…
[all …]
Dregbankselect-fcanonicalize.mir15 ; CHECK: [[FCANONICALIZE:%[0-9]+]]:vgpr(s32) = G_FCANONICALIZE [[COPY1]]
16 ; CHECK: $vgpr0 = COPY [[FCANONICALIZE]](s32)
31 ; CHECK: [[FCANONICALIZE:%[0-9]+]]:vgpr(s32) = G_FCANONICALIZE [[COPY]]
32 ; CHECK: $vgpr0 = COPY [[FCANONICALIZE]](s32)
Dlegalize-fmaxnum.mir18 ; SI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
20 ; SI: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
25 ; VI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
27 ; VI: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
32 ; GFX9: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
34 ; GFX9: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
109 ; SI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
110 ; SI: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY]], [[FCANONICALIZE]]
115 ; VI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
116 ; VI: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[COPY]], [[FCANONICALIZE]]
[all …]
Dlegalize-fminnum.mir18 ; SI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
20 ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
25 ; VI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
27 ; VI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
32 ; GFX9: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
34 ; GFX9: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
109 ; SI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
110 ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[FCANONICALIZE]]
115 ; VI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
116 ; VI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[FCANONICALIZE]]
[all …]
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h261 FCANONICALIZE, enumerator
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h373 FCANONICALIZE, enumerator
DBasicTTIImpl.h1247 ISDs.push_back(ISD::FCANONICALIZE);
/external/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h477 FCANONICALIZE, enumerator
DBasicTTIImpl.h1442 ISDs.push_back(ISD::FCANONICALIZE); in getTypeBasedIntrinsicInstrCost()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp205 case ISD::FCANONICALIZE: return "fcanonicalize"; in getOperationName()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp263 case ISD::FCANONICALIZE: return "fcanonicalize"; in getOperationName()
DLegalizeVectorTypes.cpp104 case ISD::FCANONICALIZE: in ScalarizeVectorResult()
896 case ISD::FCANONICALIZE: in SplitVectorResult()
1974 case ISD::FCANONICALIZE: in SplitVectorOperand()
2845 case ISD::FCANONICALIZE: in WidenVectorResult()
DLegalizeVectorOps.cpp454 case ISD::FCANONICALIZE: in LegalizeOp()
DLegalizeFloatTypes.cpp2123 case ISD::FCANONICALIZE: R = PromoteFloatRes_UnaryOp(N); break; in PromoteFloatResult()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp267 case ISD::FCANONICALIZE: return "fcanonicalize"; in getOperationName()
DLegalizeVectorOps.cpp451 case ISD::FCANONICALIZE: in LegalizeOp()
DLegalizeFloatTypes.cpp2230 case ISD::FCANONICALIZE: R = PromoteFloatRes_UnaryOp(N); break; in PromoteFloatResult()
2595 case ISD::FCANONICALIZE: R = SoftPromoteHalfRes_UnaryOp(N); break; in SoftPromoteHalfResult()
DLegalizeVectorTypes.cpp107 case ISD::FCANONICALIZE: in ScalarizeVectorResult()
957 case ISD::FCANONICALIZE: in SplitVectorResult()
3005 case ISD::FCANONICALIZE: in WidenVectorResult()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp632 setOperationAction(ISD::FCANONICALIZE, MVT::v2f16, Legal); in SITargetLowering()
661 setOperationAction(ISD::FCANONICALIZE, MVT::v4f16, Custom); in SITargetLowering()
737 setTargetDAGCombine(ISD::FCANONICALIZE); in SITargetLowering()
4082 case ISD::FCANONICALIZE: in LowerOperation()
8599 case ISD::FCANONICALIZE: in fp16SrcZerosHighBits()
8744 if (Opcode == ISD::FCANONICALIZE) in isCanonicalized()
8973 NewElts[I] = DAG.getNode(ISD::FCANONICALIZE, SL, EltVT, Op); in performFCanonicalizeCombine()
9006 SDValue Canon0 = DAG.getNode(ISD::FCANONICALIZE, SL, VT, in performFCanonicalizeCombine()
10057 case ISD::FCANONICALIZE: in PerformDAGCombine()
DAMDGPUISelLowering.cpp432 setOperationAction(ISD::FCANONICALIZE, VT, Expand); in AMDGPUTargetLowering()
526 case ISD::FCANONICALIZE: in fnegFoldsIntoOp()
3810 case ISD::FCANONICALIZE: in performFNegCombine()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp734 setOperationAction(ISD::FCANONICALIZE, MVT::v2f16, Legal); in SITargetLowering()
768 setOperationAction(ISD::FCANONICALIZE, MVT::v4f16, Custom); in SITargetLowering()
851 setTargetDAGCombine(ISD::FCANONICALIZE); in SITargetLowering()
4563 case ISD::FCANONICALIZE: in LowerOperation()
9313 case ISD::FCANONICALIZE: in fp16SrcZerosHighBits()
9463 if (Opcode == ISD::FCANONICALIZE) in isCanonicalized()
9696 NewElts[I] = DAG.getNode(ISD::FCANONICALIZE, SL, EltVT, Op); in performFCanonicalizeCombine()
9729 SDValue Canon0 = DAG.getNode(ISD::FCANONICALIZE, SL, VT, in performFCanonicalizeCombine()
10787 case ISD::FCANONICALIZE: in PerformDAGCombine()
DAMDGPUISelLowering.cpp498 setOperationAction(ISD::FCANONICALIZE, VT, Expand); in AMDGPUTargetLowering()
596 case ISD::FCANONICALIZE: in fnegFoldsIntoOp()
3797 case ISD::FCANONICALIZE: in performFNegCombine()
/external/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp233 setTargetDAGCombine(ISD::FCANONICALIZE); in SITargetLowering()
3047 case ISD::FCANONICALIZE: in PerformDAGCombine()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td440 def fcanonicalize : SDNode<"ISD::FCANONICALIZE", SDTFPUnaryOp>;
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DTargetSelectionDAG.td454 def fcanonicalize : SDNode<"ISD::FCANONICALIZE", SDTFPUnaryOp>;

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