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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenAsmWriter.inc8212 // (BC1F FCC0, brtarget:$offset) - 31
8213 {AliasPatternCond::K_Reg, Mips::FCC0},
8214 // (BC1FL FCC0, brtarget:$offset) - 32
8215 {AliasPatternCond::K_Reg, Mips::FCC0},
8216 // (BC1F_MM FCC0, brtarget:$offset) - 33
8217 {AliasPatternCond::K_Reg, Mips::FCC0},
8218 // (BC1T FCC0, brtarget:$offset) - 34
8219 {AliasPatternCond::K_Reg, Mips::FCC0},
8220 // (BC1TL FCC0, brtarget:$offset) - 35
8221 {AliasPatternCond::K_Reg, Mips::FCC0},
[all …]
/external/swiftshader/third_party/subzero/src/
DIceAssemblerMIPS32.cpp443 emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, in c_eq_d()
449 emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, in c_eq_s()
455 emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, in c_ole_d()
461 emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, in c_ole_s()
467 emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, in c_olt_d()
473 emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, in c_olt_s()
479 emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, in c_ueq_d()
485 emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, in c_ueq_s()
491 emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, in c_ule_d()
497 emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, in c_ule_s()
[all …]
DIceTargetLoweringMIPS32.cpp3974 Operand *FCC0 = OperandMIPS32FCC::create(getFunc(), OperandMIPS32FCC::FCC0); in lowerFcmp() local
3995 _movf(DestR, Zero, FCC0); in lowerFcmp()
4006 _movt(DestR, Zero, FCC0); in lowerFcmp()
4017 _movt(DestR, Zero, FCC0); in lowerFcmp()
4028 _movf(DestR, Zero, FCC0); in lowerFcmp()
4039 _movf(DestR, Zero, FCC0); in lowerFcmp()
4050 _movt(DestR, Zero, FCC0); in lowerFcmp()
4061 _movt(DestR, Zero, FCC0); in lowerFcmp()
4072 _movf(DestR, Zero, FCC0); in lowerFcmp()
4083 _movt(DestR, Zero, FCC0); in lowerFcmp()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsInstrFPU.td261 let Defs = [FCC0];
830 (!cast<Instruction>("C_F_"#NAME) FCC0,
833 (!cast<Instruction>("C_UN_"#NAME) FCC0,
836 (!cast<Instruction>("C_EQ_"#NAME) FCC0,
839 (!cast<Instruction>("C_UEQ_"#NAME) FCC0,
842 (!cast<Instruction>("C_OLT_"#NAME) FCC0,
845 (!cast<Instruction>("C_ULT_"#NAME) FCC0,
848 (!cast<Instruction>("C_OLE_"#NAME) FCC0,
851 (!cast<Instruction>("C_ULE_"#NAME) FCC0,
854 (!cast<Instruction>("C_SF_"#NAME) FCC0,
[all …]
DMipsISelLowering.cpp669 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); in createCMovFP() local
672 True.getValueType(), True, FCC0, False, Cond); in createCMovFP()
2037 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); in lowerBRCOND() local
2039 FCC0, Dest, CondRes); in lowerBRCOND()
/external/llvm-project/llvm/lib/Target/Mips/
DMipsInstrFPU.td264 let Defs = [FCC0];
863 (!cast<Instruction>("C_F_"#NAME) FCC0,
866 (!cast<Instruction>("C_UN_"#NAME) FCC0,
869 (!cast<Instruction>("C_EQ_"#NAME) FCC0,
872 (!cast<Instruction>("C_UEQ_"#NAME) FCC0,
875 (!cast<Instruction>("C_OLT_"#NAME) FCC0,
878 (!cast<Instruction>("C_ULT_"#NAME) FCC0,
881 (!cast<Instruction>("C_OLE_"#NAME) FCC0,
884 (!cast<Instruction>("C_ULE_"#NAME) FCC0,
887 (!cast<Instruction>("C_SF_"#NAME) FCC0,
[all …]
DMipsISelLowering.cpp670 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); in createCMovFP() local
673 True.getValueType(), True, FCC0, False, Cond); in createCMovFP()
2035 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); in lowerBRCOND() local
2037 FCC0, Dest, CondRes); in lowerBRCOND()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsInstPrinter.cpp244 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS); in printAlias()
247 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS); in printAlias()
/external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
DMipsInstPrinter.cpp244 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS); in printAlias()
247 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS); in printAlias()
/external/llvm/lib/Target/Mips/InstPrinter/
DMipsInstPrinter.cpp249 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS); in printAlias()
252 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS); in printAlias()
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td490 def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
491 def : InstAlias<"fcmpd $rs1, $rs2", (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)>;
492 def : InstAlias<"fcmpq $rs1, $rs2", (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)>,
495 def : InstAlias<"fcmpes $rs1, $rs2", (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
496 def : InstAlias<"fcmped $rs1, $rs2", (V9FCMPED FCC0, DFPRegs:$rs1,
498 def : InstAlias<"fcmpeq $rs1, $rs2", (V9FCMPEQ FCC0, QFPRegs:$rs1,
DSparcInstrInfo.td451 let usesCustomInserter = 1, Uses = [FCC0] in {
866 let Uses = [FCC0] in {
1293 let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in {
1363 let Uses = [FCC0], intcc = 0, cc = 0b00 in {
1396 let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in {
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td507 def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
508 def : InstAlias<"fcmpd $rs1, $rs2", (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)>;
509 def : InstAlias<"fcmpq $rs1, $rs2", (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)>,
512 def : InstAlias<"fcmpes $rs1, $rs2", (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
513 def : InstAlias<"fcmped $rs1, $rs2", (V9FCMPED FCC0, DFPRegs:$rs1,
515 def : InstAlias<"fcmpeq $rs1, $rs2", (V9FCMPEQ FCC0, QFPRegs:$rs1,
DSparcInstrInfo.td471 let usesCustomInserter = 1, Uses = [FCC0] in {
871 let Uses = [FCC0] in {
1299 let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in {
1369 let Uses = [FCC0], intcc = 0, cc = 0b00 in {
1402 let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in {
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcInstrAliases.td507 def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
508 def : InstAlias<"fcmpd $rs1, $rs2", (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)>;
509 def : InstAlias<"fcmpq $rs1, $rs2", (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)>,
512 def : InstAlias<"fcmpes $rs1, $rs2", (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
513 def : InstAlias<"fcmped $rs1, $rs2", (V9FCMPED FCC0, DFPRegs:$rs1,
515 def : InstAlias<"fcmpeq $rs1, $rs2", (V9FCMPEQ FCC0, QFPRegs:$rs1,
DSparcInstrInfo.td471 let usesCustomInserter = 1, Uses = [FCC0] in {
871 let Uses = [FCC0] in {
1299 let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in {
1369 let Uses = [FCC0], intcc = 0, cc = 0b00 in {
1402 let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in {
/external/llvm/lib/Target/Sparc/InstPrinter/
DSparcInstPrinter.cpp88 || (MI->getOperand(0).getReg() != SP::FCC0)) in printSparcAliasInstr()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/MCTargetDesc/
DSparcInstPrinter.cpp88 || (MI->getOperand(0).getReg() != SP::FCC0)) in printSparcAliasInstr()
/external/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/
DSparcInstPrinter.cpp89 || (MI->getOperand(0).getReg() != SP::FCC0)) in printSparcAliasInstr()
/external/llvm/lib/Target/Mips/
DMipsInstrFPU.td230 let Defs = [FCC0];
593 def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>,
595 def : MipsInstAlias<"bc1tl $offset", (BC1TL FCC0, brtarget:$offset)>,
597 def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>,
599 def : MipsInstAlias<"bc1fl $offset", (BC1FL FCC0, brtarget:$offset)>,
DMipsISelLowering.cpp570 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); in createCMovFP() local
573 True.getValueType(), True, FCC0, False, Cond); in createCMovFP()
1716 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); in lowerBRCOND() local
1718 FCC0, Dest, CondRes); in lowerBRCOND()
DMipsFastISel.cpp707 Mips::FCC0, RegState::ImplicitDefine); in emitCmp()
710 .addReg(Mips::FCC0) in emitCmp()
/external/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp108 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp101 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
/external/llvm-project/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp101 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };

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