| /external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
| D | regbank-select.mir | 116 ; inputs is an FPR, then it's fewer copies to just do a FCSEL.
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 44 FCSEL, // Conditional move instruction. enumerator
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| D | AArch64SchedM1.td | 256 def : InstRW<[M1WriteNEONH], (instregex "^FCSEL[DS]rrr")>;
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| D | AArch64SchedVulcan.td | 423 def : InstRW<[VulcanWrite_4Cyc_F01], (instregex "^FCSEL")>;
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| D | AArch64SchedCyclone.td | 464 // FCSEL is a WriteF.
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| D | AArch64ISelLowering.cpp | 843 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL"; in getTargetNodeName()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 44 FCSEL, // Conditional move instruction. enumerator
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| D | AArch64SchedCyclone.td | 465 // FCSEL is a WriteF.
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| D | AArch64SchedExynosM3.td | 542 def : InstRW<[M3WriteNEONH], (instregex "^FCSEL[DS]rrr")>;
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| D | AArch64SchedExynosM5.td | 712 def : InstRW<[M5WriteNEONH], (instregex "^FCSEL[HSD]rrr")>;
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| D | AArch64SchedExynosM4.td | 653 def : InstRW<[M4WriteNEONH], (instregex "^FCSEL[HSD]rrr")>;
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| D | AArch64SchedFalkorDetails.td | 1118 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^FCSEL(S|D)rrr$")>;
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| D | AArch64SchedThunderX2T99.td | 1188 def : InstRW<[THX2T99Write_4Cyc_F01], (instregex "^FCSEL")>;
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 64 FCSEL, // Conditional move instruction. enumerator
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| D | AArch64SchedCyclone.td | 466 // FCSEL is a WriteF.
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| D | AArch64SchedTSV110.td | 459 def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FCSEL(S|D)rrr$")>;
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| D | AArch64SchedExynosM3.td | 543 def : InstRW<[M3WriteNEONH], (instregex "^FCSEL[DS]rrr")>;
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| D | AArch64SchedExynosM4.td | 654 def : InstRW<[M4WriteNEONH], (instregex "^FCSEL[HSD]rrr")>;
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| D | AArch64SchedExynosM5.td | 713 def : InstRW<[M5WriteNEONH], (instregex "^FCSEL[HSD]rrr")>;
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| D | AArch64SchedFalkorDetails.td | 1118 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^FCSEL(S|D)rrr$")>;
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| D | AArch64SchedThunderX3T110.td | 1296 def : InstRW<[THX3T110Write_3_4Cyc_F23_F0123], (instregex "^FCSEL")>;
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| D | AArch64SchedThunderX2T99.td | 1188 def : InstRW<[THX2T99Write_4Cyc_F01], (instregex "^FCSEL")>;
|
| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 1547 FCSEL = FCSEL_s enumerator
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| D | assembler-aarch64.cc | 3017 Emit(FPType(vd) | FCSEL | Rm(vm) | Cond(cond) | Rn(vn) | Rd(vd)); in fcsel()
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 3622 ### FCSEL ### subsection
|