| /external/llvm-project/llvm/lib/Target/Sparc/ |
| D | LeonFeatures.td | 58 "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store"
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| D | SparcInstrInfo.td | 1274 // FDIVS generates an erratum on LEON processors, so by disabling this instruction
1276 def FDIVS : F3_3<2, 0b110100, 0b001001101,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | LeonFeatures.td | 58 "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store"
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| D | SparcInstrInfo.td | 1274 // FDIVS generates an erratum on LEON processors, so by disabling this instruction
1276 def FDIVS : F3_3<2, 0b110100, 0b001001101,
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| /external/llvm/lib/Target/Sparc/ |
| D | LeonFeatures.td | 72 "LEON3 erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD "
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| D | LeonPasses.cpp | 862 case SP::FDIVS: in runOnMachineFunction()
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| D | SparcInstrInfo.td | 1268 // FDIVS generates an erratum on LEON processors, so by disabling this instruction
1270 def FDIVS : F3_3<2, 0b110100, 0b001001101,
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenSubtargetInfo.inc | 3660 { 1, 49, 58, 438, 441 }, // 270 FDIVS
3979 { 1, 94, 95, 0, 0 }, // 270 FDIVS
4298 { 1, 116, 117, 0, 0 }, // 270 FDIVS
4617 { 1, 140, 141, 0, 0 }, // 270 FDIVS
4936 { 1, 160, 161, 0, 0 }, // 270 FDIVS
5255 { 1, 185, 186, 1042, 1045 }, // 270 FDIVS
5574 { 1, 203, 205, 1450, 1453 }, // 270 FDIVS
5893 { 1, 235, 237, 1898, 1901 }, // 270 FDIVS
6212 { 1, 274, 276, 2417, 2420 }, // 270 FDIVS
6531 { 1, 321, 323, 3083, 3086 }, // 270 FDIVS
[all …]
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| D | PPCGenMCCodeEmitter.inc | 931 UINT64_C(3959423012), // FDIVS
3404 case PPC::FDIVS:
7341 CEFBS_None, // FDIVS = 918
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| D | PPCGenInstrInfo.inc | 933 FDIVS = 918,
2587 FDIVS = 270,
3902 …, 4, 270, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #918 = FDIVS
12645 { PPC::FDIVS_rec, PPC::FDIVS },
12847 { PPC::FDIVS, PPC::FDIVS_rec },
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| D | PPCGenFastISel.inc | 2017 return fastEmitInst_rr(PPC::FDIVS, &PPC::F4RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeSPARC_common.c | 144 #define FDIVS (OPC1(0x2) | OPC3(0x34) | DOP(0x4d)) macro
1225 …FAIL_IF(push_inst(compiler, SELECT_FOP(op, FDIVS, FDIVD) | FD(dst_r) | FS1(src1) | FS2(src2), MOVA… in sljit_emit_fop2()
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| D | sljitNativePPC_common.c | 176 #define FDIVS (HI(59) | LO(18)) macro
1856 FAIL_IF(push_inst(compiler, SELECT_FOP(op, FDIVS, FDIV) | FD(dst_r) | FA(src1) | FB(src2))); in sljit_emit_fop2()
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 221 FDIVS, enumerator
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| D | X86IntrinsicsInfo.h | 577 X86ISD::FDIVS, X86ISD::FDIVS_RND),
579 X86ISD::FDIVS, X86ISD::FDIVS_RND),
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| D | X86InstrFragmentsSIMD.td | 523 def X86fdivs : SDNode<"X86ISD::FDIVS", SDTFPBinOp>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 577 X86ISD::FDIVS, X86ISD::FDIVS_RND),
579 X86ISD::FDIVS, X86ISD::FDIVS_RND),
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| D | X86ISelLowering.h | 210 FDIV_RND, FDIVS, FDIVS_RND, enumerator
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| D | X86InstrFragmentsSIMD.td | 514 def X86fdivs : SDNode<"X86ISD::FDIVS", SDTFPBinOp>;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | P9InstrResources.td | 1204 FDIVS
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | P9InstrResources.td | 1205 FDIVS
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| /external/capstone/arch/Sparc/ |
| D | SparcGenDisassemblerTables.inc | 626 /* 2409 */ MCD_OPC_Decode, 167, 1, 26, // Opcode: FDIVS
|
| /external/llvm-project/llvm/lib/Target/VE/ |
| D | VEInstrInfo.td | 1356 defm FDIVS : RRFm<"fdiv.s", 0x5D, F32, f32, fdiv, simm7fp, mimmfp32>;
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| /external/capstone/arch/PowerPC/ |
| D | PPCGenAsmWriter.inc | 532 23039U, // FDIVS
2054 0U, // FDIVS
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| D | PPCGenDisassemblerTables.inc | 1587 /* 6547 */ MCD_OPC_Decode, 128, 4, 87, // Opcode: FDIVS
|