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Searched refs:FFLOOR (Results 1 – 25 of 87) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-ffloor.mir14 ; SI: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[COPY]]
15 ; SI: $vgpr0 = COPY [[FFLOOR]](s32)
18 ; VI: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[COPY]]
19 ; VI: $vgpr0 = COPY [[FFLOOR]](s32)
22 ; GFX9: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[COPY]]
23 ; GFX9: $vgpr0 = COPY [[FFLOOR]](s32)
47 ; VI: [[FFLOOR:%[0-9]+]]:_(s64) = G_FFLOOR [[COPY]]
48 ; VI: $vgpr0_vgpr1 = COPY [[FFLOOR]](s64)
51 ; GFX9: [[FFLOOR:%[0-9]+]]:_(s64) = G_FFLOOR [[COPY]]
52 ; GFX9: $vgpr0_vgpr1 = COPY [[FFLOOR]](s64)
[all …]
Dinst-select-ffloor.s16.mir18 ; VI: [[FFLOOR:%[0-9]+]]:sreg_32(s16) = G_FFLOOR [[TRUNC]]
19 ; VI: [[COPY1:%[0-9]+]]:sreg_32(s32) = COPY [[FFLOOR]](s16)
87 ; SI: [[FFLOOR:%[0-9]+]]:vgpr(s16) = G_FFLOOR [[FNEG]]
88 ; SI: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FFLOOR]](s16)
Dlegalize-fptosi.mir212 ; VI: [[FFLOOR:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL]]
213 ; VI: [[FMA:%[0-9]+]]:_(s64) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
214 ; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FFLOOR]](s64)
270 ; VI: [[FFLOOR:%[0-9]+]]:_(s64) = nnan G_FFLOOR [[FMUL]]
271 ; VI: [[FMA:%[0-9]+]]:_(s64) = nnan G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
272 ; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FFLOOR]](s64)
356 ; VI: [[FFLOOR:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL]]
357 ; VI: [[FMA:%[0-9]+]]:_(s64) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
358 ; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FFLOOR]](s64)
Dlegalize-fptoui.mir212 ; VI: [[FFLOOR:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL]]
213 ; VI: [[FMA:%[0-9]+]]:_(s64) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
214 ; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FFLOOR]](s64)
270 ; VI: [[FFLOOR:%[0-9]+]]:_(s64) = nnan G_FFLOOR [[FMUL]]
271 ; VI: [[FMA:%[0-9]+]]:_(s64) = nnan G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
272 ; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FFLOOR]](s64)
356 ; VI: [[FFLOOR:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL]]
357 ; VI: [[FMA:%[0-9]+]]:_(s64) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
358 ; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FFLOOR]](s64)
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h526 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, enumerator
DBasicTTIImpl.h782 ISDs.push_back(ISD::FFLOOR); in getIntrinsicInstrCost()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DConstrainedOps.def62 FUNCTION(floor, 1, 0, experimental_constrained_floor, FFLOOR)
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h642 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, enumerator
/external/llvm-project/llvm/include/llvm/IR/
DConstrainedOps.def76 DAG_FUNCTION(floor, 1, 0, experimental_constrained_floor, FFLOOR)
/external/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h812 FFLOOR, enumerator
/external/llvm/lib/Target/PowerPC/
DPPCCTRLoops.cpp302 case Intrinsic::floor: Opcode = ISD::FFLOOR; break; in mightUseCTR()
348 Opcode = ISD::FFLOOR; break; in mightUseCTR()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCTargetTransformInfo.cpp312 case Intrinsic::floor: Opcode = ISD::FFLOOR; break; in mightUseCTR()
364 Opcode = ISD::FFLOOR; break; in mightUseCTR()
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCTargetTransformInfo.cpp471 case Intrinsic::floor: Opcode = ISD::FFLOOR; break; in mightUseCTR()
571 Opcode = ISD::FFLOOR; break; in mightUseCTR()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp163 case ISD::FFLOOR: return "ffloor"; in getOperationName()
DLegalizeFloatTypes.cpp86 case ISD::FFLOOR: R = SoftenFloatRes_FFLOOR(N); break; in SoftenFloatResult()
1026 case ISD::FFLOOR: ExpandFloatRes_FFLOOR(N, Lo, Hi); break; in ExpandFloatResult()
1874 case ISD::FFLOOR: in PromoteFloatResult()
DLegalizeVectorOps.cpp323 case ISD::FFLOOR: in LegalizeOp()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp87 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp243 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); in AMDGPUTargetLowering()
280 setOperationAction(ISD::FFLOOR, MVT::f64, Custom); in AMDGPUTargetLowering()
418 setOperationAction(ISD::FFLOOR, VT, Expand); in AMDGPUTargetLowering()
718 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG); in LowerOperation()
2056 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul); in LowerFP64_TO_INT()
/external/mesa3d/src/broadcom/compiler/
Dv3d_compiler.h1147 VIR_A_ALU1(FFLOOR) in VIR_A_ALU2()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp203 case ISD::FFLOOR: return "ffloor"; in getOperationName()
DLegalizeFloatTypes.cpp87 case ISD::FFLOOR: R = SoftenFloatRes_FFLOOR(N); break; in SoftenFloatResult()
1149 case ISD::FFLOOR: ExpandFloatRes_FFLOOR(N, Lo, Hi); break; in ExpandFloatResult()
2112 case ISD::FFLOOR: in PromoteFloatResult()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp205 case ISD::FFLOOR: return "ffloor"; in getOperationName()
DLegalizeFloatTypes.cpp87 case ISD::FFLOOR: R = SoftenFloatRes_FFLOOR(N); break; in SoftenFloatResult()
1187 case ISD::FFLOOR: ExpandFloatRes_FFLOOR(N, Lo, Hi); break; in ExpandFloatResult()
2218 case ISD::FFLOOR: in PromoteFloatResult()
2582 case ISD::FFLOOR: in SoftPromoteHalfResult()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp99 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
192 for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, in WebAssemblyTargetLowering()
/external/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp99 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
182 for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, in WebAssemblyTargetLowering()

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