| /external/one-true-awk/ |
| D | awk.h | 132 #define FLD 0100 /* this is a field $1, $2, ... */ macro
215 #define isfld(n) ((n)->tval & FLD)
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| D | lib.c | 61 static Cell dollar1 = { OCELL, CFLD, NULL, EMPTY, 0.0, FLD|STR|DONTFREE, NULL, NULL };
355 fldtab[i]->tval = FLD | STR | DONTFREE; in fldbld()
377 fldtab[i]->tval = FLD | STR; in fldbld()
395 fldtab[i]->tval = FLD | STR | DONTFREE; in fldbld()
438 p->tval = FLD | STR | DONTFREE; in cleanfld()
520 fldtab[i]->tval = FLD | STR | DONTFREE; in refldbld()
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| D | tran.c | 638 { "FLD", FLD }, in flags2str()
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| D | run.c | 334 y->tval = x->tval & ~(CON|FLD|REC); in copycell()
1131 if (x == y && !(x->tval & (FLD|REC)) && x != nfloc) in assign()
|
| /external/pcre/dist2/src/ |
| D | pcre2test.c | 1071 #define FLD(a,b) ((test_mode == PCRE8_MODE)? G(a,8)->b : \ macro
1615 #define FLD(a,b) \ macro
2028 #define FLD(a,b) G(a,8)->b macro
2135 #define FLD(a,b) G(a,16)->b macro
2242 #define FLD(a,b) G(a,32)->b macro
4056 8 * (FLD(compiled_code, flags) & PCRE2_MODE_MASK)); in pattern_info()
4364 BOOL utf = (FLD(compiled_code, overall_options) & PCRE2_UTF) != 0; in callout_callback()
4412 BOOL utf = (FLD(compiled_code, overall_options) & PCRE2_UTF) != 0; in show_pattern_info()
4633 (FLD(compiled_code, flags) & PCRE2_BSR_SET) != 0) in show_pattern_info()
4637 if ((FLD(compiled_code, flags) & PCRE2_NL_SET) != 0) in show_pattern_info()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoD.td | 72 def FLD : RVInstI<0b011, OPC_LOAD_FP, (outs FPR64:$rd),
204 def : InstAlias<"fld $rd, (${rs1})", (FLD FPR64:$rd, GPR:$rs1, 0), 0>;
312 defm : LdPat<load, FLD>;
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| D | RISCVMergeBaseOffset.cpp | 220 case RISCV::FLD: in detectAndFoldOffset()
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| D | RISCVISelDAGToDAG.cpp | 227 case RISCV::FLD: in doPeepholeLoadStoreADDI()
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| D | RISCVInstrInfo.cpp | 52 case RISCV::FLD: in isLoadFromStackSlot()
157 Opcode = RISCV::FLD; in loadRegFromStackSlot()
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| D | RISCVInstrInfoC.td | 759 def : CompressPat<(FLD FPR64C:$rd, GPRC:$rs1, uimm8_lsb000:$imm),
871 def : CompressPat<(FLD FPR64:$rd, SP:$rs1, uimm9_lsb000:$imm),
|
| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoD.td | 70 def FLD : RVInstI<0b011, OPC_LOAD_FP, (outs FPR64:$rd),
211 def : InstAlias<"fld $rd, (${rs1})", (FLD FPR64:$rd, GPR:$rs1, 0), 0>;
323 defm : LdPat<load, FLD>;
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| D | RISCVMergeBaseOffset.cpp | 221 case RISCV::FLD: in detectAndFoldOffset()
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| D | RISCVInstrInfo.cpp | 53 case RISCV::FLD: in isLoadFromStackSlot()
176 Opcode = RISCV::FLD; in loadRegFromStackSlot()
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| D | RISCVISelDAGToDAG.cpp | 400 case RISCV::FLD: in doPeepholeLoadStoreADDI()
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| D | RISCVInstrInfoC.td | 764 def : CompressPat<(FLD FPR64C:$rd, GPRC:$rs1, uimm8_lsb000:$imm),
876 def : CompressPat<(FLD FPR64:$rd, SP:$rs1, uimm9_lsb000:$imm),
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 580 FLD, enumerator
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| D | X86InstrFPStack.td | 35 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
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| D | X86SchedHaswell.td | 1071 // FLD.
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 809 FLD, enumerator
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| D | X86InstrFPStack.td | 28 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
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| D | X86SchedHaswell.td | 735 // FLD.
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 677 FLD, enumerator
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| D | X86InstrFPStack.td | 29 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/AsmParser/ |
| D | RISCVAsmParser.cpp | 1858 emitLoadStoreSymbol(Inst, RISCV::FLD, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()
|
| /external/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| D | RISCVAsmParser.cpp | 2407 emitLoadStoreSymbol(Inst, RISCV::FLD, IDLoc, Out, /*HasTmpReg=*/true); in processInstruction()
|