| /external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| D | legalize-amdgcn.rsq.clamp.mir | 58 ; VI: [[FMAXNUM:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMAXNUM [[FMINNUM]], [[C1]]
59 ; VI: $vgpr0 = COPY [[FMAXNUM]](s32)
|
| D | legalize-fmaxnum.mir | 54 ; SI: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[COPY]], [[COPY1]]
55 ; SI: $vgpr0 = COPY [[FMAXNUM]](s32)
59 ; VI: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[COPY]], [[COPY1]]
60 ; VI: $vgpr0 = COPY [[FMAXNUM]](s32)
64 ; GFX9: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[COPY]], [[COPY1]]
65 ; GFX9: $vgpr0 = COPY [[FMAXNUM]](s32)
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
| D | irtranslator-fp-min-max-intrinsics.ll | 36 ; CHECK: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[COPY]], [[COPY1]]
37 ; CHECK: $s0 = COPY [[FMAXNUM]](s32)
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 532 FMINNUM, FMAXNUM, enumerator
|
| D | BasicTTIImpl.h | 774 ISDs.push_back(ISD::FMAXNUM); in getIntrinsicInstrCost()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 71 FUNCTION(maxnum, 2, 0, experimental_constrained_maxnum, FMAXNUM)
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 2407 { ISD::FMAXNUM, MVT::f32, 2 }, in getTypeBasedIntrinsicInstrCost()
2408 { ISD::FMAXNUM, MVT::v4f32, 2 }, in getTypeBasedIntrinsicInstrCost()
2409 { ISD::FMAXNUM, MVT::v8f32, 2 }, in getTypeBasedIntrinsicInstrCost()
2410 { ISD::FMAXNUM, MVT::v16f32, 2 }, in getTypeBasedIntrinsicInstrCost()
2411 { ISD::FMAXNUM, MVT::f64, 2 }, in getTypeBasedIntrinsicInstrCost()
2412 { ISD::FMAXNUM, MVT::v2f64, 2 }, in getTypeBasedIntrinsicInstrCost()
2413 { ISD::FMAXNUM, MVT::v4f64, 2 }, in getTypeBasedIntrinsicInstrCost()
2414 { ISD::FMAXNUM, MVT::v8f64, 2 }, in getTypeBasedIntrinsicInstrCost()
2476 { ISD::FMAXNUM, MVT::v8f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS in getTypeBasedIntrinsicInstrCost()
2477 { ISD::FMAXNUM, MVT::v4f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD in getTypeBasedIntrinsicInstrCost()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 652 FMINNUM, FMAXNUM, enumerator
|
| /external/llvm-project/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 85 DAG_FUNCTION(maxnum, 2, 0, experimental_constrained_maxnum, FMAXNUM)
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 826 FMAXNUM, enumerator
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 309 case Intrinsic::maxnum: Opcode = ISD::FMAXNUM; break; in mightUseCTR()
376 Opcode = ISD::FMAXNUM; break; in mightUseCTR()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 323 case Intrinsic::maxnum: Opcode = ISD::FMAXNUM; break; in mightUseCTR()
392 Opcode = ISD::FMAXNUM; break; in mightUseCTR()
|
| /external/llvm-project/llvm/docs/GlobalISel/ |
| D | GenericOpcode.rst | 438 The return value of (FMAXNUM 0.0, -0.0) could be either 0.0 or -0.0.
451 definition. This differs from FMAXNUM in the handling of signaling NaNs. If one
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 482 case Intrinsic::maxnum: Opcode = ISD::FMAXNUM; break; in mightUseCTR()
599 Opcode = ISD::FMAXNUM; break; in mightUseCTR()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 206 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in SITargetLowering()
224 setTargetDAGCombine(ISD::FMAXNUM); in SITargetLowering()
1711 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp, in LowerINTRINSIC_WO_CHAIN()
2693 case ISD::FMAXNUM: in minMaxOpcToMin3Max3Opc()
2816 if (((Opc == ISD::FMINNUM && Op0.getOpcode() == ISD::FMAXNUM) || in performMinMaxCombine()
2868 case ISD::FMAXNUM: in PerformDAGCombine()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 154 case ISD::FMAXNUM: return "fmaxnum"; in getOperationName()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 414 setOperationAction(ISD::FMAXNUM, MVT::f32, Custom); in SITargetLowering()
416 setOperationAction(ISD::FMAXNUM, MVT::f64, Custom); in SITargetLowering()
601 setOperationAction(ISD::FMAXNUM, MVT::f16, Custom); in SITargetLowering()
610 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Expand); in SITargetLowering()
656 setOperationAction(ISD::FMAXNUM, MVT::v2f16, Custom); in SITargetLowering()
660 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Custom); in SITargetLowering()
723 setTargetDAGCombine(ISD::FMAXNUM); in SITargetLowering()
4085 case ISD::FMAXNUM: in LowerOperation()
5810 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp, in LowerINTRINSIC_WO_CHAIN()
8623 case ISD::FMAXNUM: in fp16SrcZerosHighBits()
[all …]
|
| D | AMDGPUISelLowering.cpp | 259 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in AMDGPUTargetLowering()
405 setOperationAction(ISD::FMAXNUM, VT, Expand); in AMDGPUTargetLowering()
519 case ISD::FMAXNUM: in fnegFoldsIntoOp()
3646 case ISD::FMAXNUM: in inverseMinMax()
3649 return ISD::FMAXNUM; in inverseMinMax()
3763 case ISD::FMAXNUM: in performFNegCombine()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | GenericOpcodes.td | 536 // FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
559 // FMINNUM/FMAXNUM in the handling of signaling NaNs. If one input is a
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 409 case ISD::FMAXNUM: in LegalizeOp()
809 case ISD::FMAXNUM: in Expand()
|
| D | SelectionDAGDumper.cpp | 186 case ISD::FMAXNUM: return "fmaxnum"; in getOperationName()
|
| D | LegalizeFloatTypes.cpp | 71 case ISD::FMAXNUM: R = SoftenFloatRes_FMAXNUM(N); break; in SoftenFloatResult()
1171 case ISD::FMAXNUM: ExpandFloatRes_FMAXNUM(N, Lo, Hi); break; in ExpandFloatResult()
2237 case ISD::FMAXNUM: in PromoteFloatResult()
2602 case ISD::FMAXNUM: in SoftPromoteHalfResult()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 505 setOperationAction(ISD::FMAXNUM, MVT::f32, Custom); in SITargetLowering()
507 setOperationAction(ISD::FMAXNUM, MVT::f64, Custom); in SITargetLowering()
698 setOperationAction(ISD::FMAXNUM, MVT::f16, Custom); in SITargetLowering()
707 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Expand); in SITargetLowering()
763 setOperationAction(ISD::FMAXNUM, MVT::v2f16, Custom); in SITargetLowering()
767 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Custom); in SITargetLowering()
837 setTargetDAGCombine(ISD::FMAXNUM); in SITargetLowering()
4567 case ISD::FMAXNUM: in LowerOperation()
6477 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp, in LowerINTRINSIC_WO_CHAIN()
9337 case ISD::FMAXNUM: in fp16SrcZerosHighBits()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 184 case ISD::FMAXNUM: return "fmaxnum"; in getOperationName()
|
| D | LegalizeVectorOps.cpp | 413 case ISD::FMAXNUM: in LegalizeOp()
928 case ISD::FMAXNUM: in Expand()
|