| /external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| D | legalize-fmaxnum.mir | 20 ; SI: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
21 ; SI: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
27 ; VI: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
28 ; VI: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
34 ; GFX9: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
35 ; GFX9: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
81 ; SI: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
82 ; SI: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
86 ; VI: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
87 ; VI: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
[all …]
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| D | legalize-amdgcn.rsq.clamp.mir | 28 ; VI: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[C1]]
29 ; VI: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 658 FMINNUM_IEEE, FMAXNUM_IEEE, enumerator
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| D | TargetLowering.h | 2262 case ISD::FMAXNUM_IEEE: in isCommutativeBinOp()
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 833 FMAXNUM_IEEE, enumerator
|
| D | TargetLowering.h | 2429 case ISD::FMAXNUM_IEEE: in isCommutativeBinOp()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | GenericOpcodes.td | 557 // FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on
576 // as less than 0.0. While FMINNUM_IEEE/FMAXNUM_IEEE follow IEEE 754-2008
|
| D | TargetSelectionDAG.td | 447 def fmaxnum_ieee : SDNode<"ISD::FMAXNUM_IEEE", SDTFPBinOp,
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 187 case ISD::FMAXNUM_IEEE: return "fmaxnum_ieee"; in getOperationName()
|
| D | LegalizeVectorOps.cpp | 415 case ISD::FMAXNUM_IEEE: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 117 case ISD::FMAXNUM_IEEE: in ScalarizeVectorResult()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 189 case ISD::FMAXNUM_IEEE: return "fmaxnum_ieee"; in getOperationName()
|
| D | LegalizeVectorOps.cpp | 411 case ISD::FMAXNUM_IEEE: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 120 case ISD::FMAXNUM_IEEE: in ScalarizeVectorResult()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 423 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal); in SITargetLowering()
425 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal); in SITargetLowering()
603 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f16, Legal); in SITargetLowering()
607 setOperationAction(ISD::FMAXNUM_IEEE, MVT::v4f16, Custom); in SITargetLowering()
630 setOperationAction(ISD::FMAXNUM_IEEE, MVT::v2f16, Legal); in SITargetLowering()
725 setTargetDAGCombine(ISD::FMAXNUM_IEEE); in SITargetLowering()
4102 case ISD::FMAXNUM_IEEE: in LowerOperation()
8809 case ISD::FMAXNUM_IEEE: in isCanonicalized()
9021 case ISD::FMAXNUM_IEEE: in minMaxOpcToMin3Max3Opc()
9198 (Opc == ISD::FMINNUM_IEEE && Op0.getOpcode() == ISD::FMAXNUM_IEEE) || in performMinMaxCombine()
[all …]
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| D | AMDGPUISelLowering.cpp | 521 case ISD::FMAXNUM_IEEE: in fnegFoldsIntoOp()
3650 case ISD::FMAXNUM_IEEE: in inverseMinMax()
3653 return ISD::FMAXNUM_IEEE; in inverseMinMax()
3765 case ISD::FMAXNUM_IEEE: in performFNegCombine()
|
| /external/llvm-project/llvm/docs/GlobalISel/ |
| D | GenericOpcode.rst | 465 FMAXNUM_IEEE follow IEEE 754-2008 semantics, FMAXIMUM follows IEEE 754-2018
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 514 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal); in SITargetLowering()
516 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal); in SITargetLowering()
700 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f16, Legal); in SITargetLowering()
704 setOperationAction(ISD::FMAXNUM_IEEE, MVT::v4f16, Custom); in SITargetLowering()
732 setOperationAction(ISD::FMAXNUM_IEEE, MVT::v2f16, Legal); in SITargetLowering()
839 setTargetDAGCombine(ISD::FMAXNUM_IEEE); in SITargetLowering()
4584 case ISD::FMAXNUM_IEEE: in LowerOperation()
9526 case ISD::FMAXNUM_IEEE: in isCanonicalized()
9744 case ISD::FMAXNUM_IEEE: in minMaxOpcToMin3Max3Opc()
9920 (Opc == ISD::FMINNUM_IEEE && Op0.getOpcode() == ISD::FMAXNUM_IEEE) || in performMinMaxCombine()
[all …]
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| D | AMDGPUISelLowering.cpp | 591 case ISD::FMAXNUM_IEEE: in fnegFoldsIntoOp()
3629 case ISD::FMAXNUM_IEEE: in inverseMinMax()
3632 return ISD::FMAXNUM_IEEE; in inverseMinMax()
3745 case ISD::FMAXNUM_IEEE: in performFNegCombine()
|
| /external/llvm-project/llvm/include/llvm/Target/ |
| D | GenericOpcodes.td | 727 // FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on
746 // as less than 0.0. While FMINNUM_IEEE/FMAXNUM_IEEE follow IEEE 754-2008
|
| D | TargetSelectionDAG.td | 454 def fmaxnum_ieee : SDNode<"ISD::FMAXNUM_IEEE", SDTFPBinOp,
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 642 setOperationAction(ISD::FMAXNUM_IEEE, VT, Expand); in initActions()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 752 setOperationAction(ISD::FMAXNUM_IEEE, VT, Expand); in initActions()
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenFastISel.inc | 2103 // FastEmit functions for ISD::FMAXNUM_IEEE.
3286 …case ISD::FMAXNUM_IEEE: return fastEmit_ISD_FMAXNUM_IEEE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsK…
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 563 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal); in PPCTargetLowering()
564 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal); in PPCTargetLowering()
|