Home
last modified time | relevance | path

Searched refs:FMINNUM_IEEE (Results 1 – 25 of 38) sorted by relevance

12

/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-fminnum.mir20 ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
21 ; SI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
27 ; VI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
28 ; VI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
34 ; GFX9: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[FCANONICALIZE1]]
35 ; GFX9: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
81 ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]]
82 ; SI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
86 ; VI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]]
87 ; VI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
[all …]
Dlegalize-amdgcn.rsq.clamp.mir26 ; VI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMINNUM_IEEE [[INT]], [[C]]
28 ; VI: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[C1]]
Dlegalize-ffloor.mir39 ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT]], [[C]]
41 ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[COPY]], [[FMINNUM_IEEE]]
69 ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = nnan G_FMINNUM_IEEE [[INT]], [[C]]
70 ; SI: [[FNEG:%[0-9]+]]:_(s64) = nnan G_FNEG [[FMINNUM_IEEE]]
97 ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = nsz G_FMINNUM_IEEE [[INT]], [[C]]
99 ; SI: [[SELECT:%[0-9]+]]:_(s64) = nsz G_SELECT [[FCMP]](s1), [[COPY]], [[FMINNUM_IEEE]]
228 ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT]], [[C]]
230 ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[UV]], [[FMINNUM_IEEE]]
Dlegalize-fptosi.mir196 ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT1]], [[C10]]
198 ; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[FMUL]], [[FMINNUM_IEEE]]
256 ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = nnan G_FMINNUM_IEEE [[INT1]], [[C10]]
257 ; SI: [[FNEG:%[0-9]+]]:_(s64) = nnan G_FNEG [[FMINNUM_IEEE]]
315 ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT1]], [[C10]]
317 ; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[FMUL]], [[FMINNUM_IEEE]]
Dlegalize-fptoui.mir196 ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT1]], [[C10]]
198 ; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[FMUL]], [[FMINNUM_IEEE]]
256 ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = nnan G_FMINNUM_IEEE [[INT1]], [[C10]]
257 ; SI: [[FNEG:%[0-9]+]]:_(s64) = nnan G_FNEG [[FMINNUM_IEEE]]
315 ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT1]], [[C10]]
317 ; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[FMUL]], [[FMINNUM_IEEE]]
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h658 FMINNUM_IEEE, FMAXNUM_IEEE, enumerator
DTargetLowering.h2261 case ISD::FMINNUM_IEEE: in isCommutativeBinOp()
/external/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h832 FMINNUM_IEEE, enumerator
DTargetLowering.h2428 case ISD::FMINNUM_IEEE: in isCommutativeBinOp()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DGenericOpcodes.td557 // FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on
576 // as less than 0.0. While FMINNUM_IEEE/FMAXNUM_IEEE follow IEEE 754-2008
DTargetSelectionDAG.td445 def fminnum_ieee : SDNode<"ISD::FMINNUM_IEEE", SDTFPBinOp,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp186 case ISD::FMINNUM_IEEE: return "fminnum_ieee"; in getOperationName()
DLegalizeVectorOps.cpp414 case ISD::FMINNUM_IEEE: in LegalizeOp()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp188 case ISD::FMINNUM_IEEE: return "fminnum_ieee"; in getOperationName()
DLegalizeVectorOps.cpp410 case ISD::FMINNUM_IEEE: in LegalizeOp()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp422 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal); in SITargetLowering()
424 setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal); in SITargetLowering()
604 setOperationAction(ISD::FMINNUM_IEEE, MVT::f16, Legal); in SITargetLowering()
606 setOperationAction(ISD::FMINNUM_IEEE, MVT::v4f16, Custom); in SITargetLowering()
629 setOperationAction(ISD::FMINNUM_IEEE, MVT::v2f16, Legal); in SITargetLowering()
724 setTargetDAGCombine(ISD::FMINNUM_IEEE); in SITargetLowering()
4101 case ISD::FMINNUM_IEEE: in LowerOperation()
8808 case ISD::FMINNUM_IEEE: in isCanonicalized()
9028 case ISD::FMINNUM_IEEE: in minMaxOpcToMin3Max3Opc()
9198 (Opc == ISD::FMINNUM_IEEE && Op0.getOpcode() == ISD::FMAXNUM_IEEE) || in performMinMaxCombine()
[all …]
DAMDGPUISelLowering.cpp520 case ISD::FMINNUM_IEEE: in fnegFoldsIntoOp()
3651 return ISD::FMINNUM_IEEE; in inverseMinMax()
3652 case ISD::FMINNUM_IEEE: in inverseMinMax()
3766 case ISD::FMINNUM_IEEE: in performFNegCombine()
/external/llvm-project/llvm/docs/GlobalISel/
DGenericOpcode.rst458 FMINNUM_IEEE follow IEEE 754-2008 semantics, FMINIMUM follows IEEE 754-2018
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp513 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal); in SITargetLowering()
515 setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal); in SITargetLowering()
701 setOperationAction(ISD::FMINNUM_IEEE, MVT::f16, Legal); in SITargetLowering()
703 setOperationAction(ISD::FMINNUM_IEEE, MVT::v4f16, Custom); in SITargetLowering()
731 setOperationAction(ISD::FMINNUM_IEEE, MVT::v2f16, Legal); in SITargetLowering()
838 setTargetDAGCombine(ISD::FMINNUM_IEEE); in SITargetLowering()
4583 case ISD::FMINNUM_IEEE: in LowerOperation()
9525 case ISD::FMINNUM_IEEE: in isCanonicalized()
9751 case ISD::FMINNUM_IEEE: in minMaxOpcToMin3Max3Opc()
9920 (Opc == ISD::FMINNUM_IEEE && Op0.getOpcode() == ISD::FMAXNUM_IEEE) || in performMinMaxCombine()
[all …]
DAMDGPUISelLowering.cpp590 case ISD::FMINNUM_IEEE: in fnegFoldsIntoOp()
3630 return ISD::FMINNUM_IEEE; in inverseMinMax()
3631 case ISD::FMINNUM_IEEE: in inverseMinMax()
3746 case ISD::FMINNUM_IEEE: in performFNegCombine()
/external/llvm-project/llvm/include/llvm/Target/
DGenericOpcodes.td727 // FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on
746 // as less than 0.0. While FMINNUM_IEEE/FMAXNUM_IEEE follow IEEE 754-2008
DTargetSelectionDAG.td452 def fminnum_ieee : SDNode<"ISD::FMINNUM_IEEE", SDTFPBinOp,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTargetLoweringBase.cpp641 setOperationAction(ISD::FMINNUM_IEEE, VT, Expand); in initActions()
/external/llvm-project/llvm/lib/CodeGen/
DTargetLoweringBase.cpp751 setOperationAction(ISD::FMINNUM_IEEE, VT, Expand); in initActions()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenFastISel.inc2149 // FastEmit functions for ISD::FMINNUM_IEEE.
3288 …case ISD::FMINNUM_IEEE: return fastEmit_ISD_FMINNUM_IEEE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsK…

12