| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | fmov-imm-licm.ll | 3 ; The purpose of this test is to check that an FMOV instruction that
5 ; We check this in two ways: by looking for the FMOV inside the loop,
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| D | arm64-crypto.ll | 52 ; <rdar://problem/14742333> Incomplete removal of unnecessary FMOV instructions in intrinsic SHA1
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| D | arm64-neon-simd-ldst-one.ll | 245 ; So LDR and FMOV should be emitted.
258 ; So LDR and FMOV should be emitted.
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedM1.td | 264 def : InstRW<[M1WriteNALU1], (instregex "^FMOV[DS][ir]")>;
265 def : InstRW<[M1WriteS4], (instregex "^FMOV[WX][DS](High)?r")>;
266 def : InstRW<[M1WriteNEONI], (instregex "^FMOV[DS][WX](High)?r")>;
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| D | AArch64ISelLowering.h | 85 FMOV, enumerator
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SchedExynosM3.td | 552 def : InstRW<[M3WriteNALU1], (instregex "^FMOV[DS][ir]")>;
557 def : InstRW<[M3WriteNALU1], (instregex "^FMOV[WX][DS]r")>;
558 def : InstRW<[M3WriteNALU1], (instregex "^FMOV[DS][WX]r")>;
559 def : InstRW<[M3WriteNEONI], (instregex "^FMOV(DX|XD)Highr")>;
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| D | AArch64SchedExynosM5.td | 722 def : InstRW<[M5WriteNALU1], (instregex "^FMOV[HSD]i")>;
723 def : InstRW<[M5WriteNALU2], (instregex "^FMOV[HSD]r")>;
724 def : InstRW<[M5WriteSA], (instregex "^FMOV[WX][HSD]r")>;
725 def : InstRW<[M5WriteFCVTA], (instregex "^FMOV[HSD][WX]r")>;
|
| D | AArch64SchedFalkorDetails.td | 1149 def : InstRW<[FalkorWr_FMOV], (instregex "^FMOV(WS|XD|XDHigh)r$")>;
1150 def : InstRW<[FalkorWr_1GTOV_0cyc], (instregex "^FMOV(S|D)i$")>; // imm fwd
1153 def : InstRW<[FalkorWr_1VTOG_1cyc], (instregex "^FMOV(SW|DX|DXHigh)r$")>;
1154 def : InstRW<[FalkorWr_1VXVY_0cyc], (instregex "^FMOV(Sr|Dr|v.*_ns)$")>; // imm fwd
|
| D | AArch64SchedExynosM4.td | 665 def : InstRW<[M4WriteNALU1], (instregex "^FMOV[HSD][ir]")>;
666 def : InstRW<[M4WriteSA], (instregex "^FMOV[WX][HSD]r")>;
667 def : InstRW<[M4WriteNEONJ], (instregex "^FMOV[HSD][WX]r")>;
|
| D | AArch64SchedTSV110.td | 490 def : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^FMOV(DX|WS|XD|SW|DXHigh|XDHigh)r$")>;
491 def : InstRW<[TSV110Wr_2cyc_1F], (instregex "^FMOV[SD][ir]$")>;
|
| D | AArch64ISelLowering.h | 150 FMOV, enumerator
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedExynosM3.td | 551 def : InstRW<[M3WriteNALU1], (instregex "^FMOV[DS][ir]")>;
556 def : InstRW<[M3WriteNALU1], (instregex "^FMOV[WX][DS]r")>;
557 def : InstRW<[M3WriteNALU1], (instregex "^FMOV[DS][WX]r")>;
558 def : InstRW<[M3WriteNEONI], (instregex "^FMOV(DX|XD)Highr")>;
|
| D | AArch64SchedExynosM5.td | 721 def : InstRW<[M5WriteNALU1], (instregex "^FMOV[HSD]i")>;
722 def : InstRW<[M5WriteNALU2], (instregex "^FMOV[HSD]r")>;
723 def : InstRW<[M5WriteSA], (instregex "^FMOV[WX][HSD]r")>;
724 def : InstRW<[M5WriteFCVTA], (instregex "^FMOV[HSD][WX]r")>;
|
| D | AArch64SchedFalkorDetails.td | 1149 def : InstRW<[FalkorWr_FMOV], (instregex "^FMOV(WS|XD|XDHigh)r$")>;
1150 def : InstRW<[FalkorWr_1GTOV_0cyc], (instregex "^FMOV(S|D)i$")>; // imm fwd
1153 def : InstRW<[FalkorWr_1VTOG_1cyc], (instregex "^FMOV(SW|DX|DXHigh)r$")>;
1154 def : InstRW<[FalkorWr_1VXVY_0cyc], (instregex "^FMOV(Sr|Dr|v.*_ns)$")>; // imm fwd
|
| D | AArch64SchedExynosM4.td | 664 def : InstRW<[M4WriteNALU1], (instregex "^FMOV[HSD][ir]")>;
665 def : InstRW<[M4WriteSA], (instregex "^FMOV[WX][HSD]r")>;
666 def : InstRW<[M4WriteNEONJ], (instregex "^FMOV[HSD][WX]r")>;
|
| D | AArch64ISelLowering.h | 85 FMOV, enumerator
|
| D | AArch64SchedKryoDetails.td | 861 (instregex "FMOV(XDHigh|DXHigh|DX)r")>;
867 (instregex "FMOV(Di|Dr|Si|Sr|SWr|WSr|XDr|v.*_ns)")>;
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-crypto.ll | 51 ; <rdar://problem/14742333> Incomplete removal of unnecessary FMOV instructions in intrinsic SHA1
|
| D | arm64-neon-simd-ldst-one.ll | 245 ; So LDR and FMOV should be emitted.
258 ; So LDR and FMOV should be emitted.
|
| /external/mesa3d/src/gallium/drivers/vc4/ |
| D | vc4_qir.h | 676 QIR_ALU1(FMOV) in QIR_ALU1() argument
|
| /external/mesa3d/src/broadcom/compiler/ |
| D | v3d_compiler.h | 1165 VIR_M_ALU1(FMOV) in VIR_A_ALU2()
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 4059 ### FMOV ### subsection
4066 ### FMOV ### subsection
4073 ### FMOV ### subsection
4080 ### FMOV ### subsection
4087 ### FMOV ### subsection
4094 ### FMOV ### subsection
4101 ### FMOV ### subsection
4108 ### FMOV ### subsection
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrFPU.td | 162 defm FMOV : ABSS_MMM<"mov.d", II_MOV_D>, ABS_FM_MM<1, 0x1>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrFPU.td | 162 defm FMOV : ABSS_MMM<"mov.d", II_MOV_D>, ABS_FM_MM<1, 0x1>;
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_64.c | 94 #define FMOV 0x1e604000 macro
1517 FAIL_IF(push_inst(compiler, (FMOV ^ inv_bits) | VD(dst_r) | VN(src))); in sljit_emit_fop1()
|