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Searched refs:FMSUB (Results 1 – 25 of 32) sorted by relevance

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/external/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
DX86InstComments.cpp325 CASE_FMA4_PACKED_RR(FMSUB) in printFMAComments()
326 CASE_FMA4_SCALAR_RR(FMSUB) in printFMAComments()
329 CASE_FMA4_PACKED_RM(FMSUB) in printFMAComments()
330 CASE_FMA4_SCALAR_RM(FMSUB) in printFMAComments()
335 CASE_FMA4_PACKED_MR(FMSUB) in printFMAComments()
336 CASE_FMA4_SCALAR_MR(FMSUB) in printFMAComments()
/external/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h1649 X86_INTRINSIC_DATA(avx512_mask3_vfmsub_pd_128, FMA_OP_MASK3, X86ISD::FMSUB, 0),
1650 X86_INTRINSIC_DATA(avx512_mask3_vfmsub_pd_256, FMA_OP_MASK3, X86ISD::FMSUB, 0),
1651 X86_INTRINSIC_DATA(avx512_mask3_vfmsub_pd_512, FMA_OP_MASK3, X86ISD::FMSUB,
1653 X86_INTRINSIC_DATA(avx512_mask3_vfmsub_ps_128, FMA_OP_MASK3, X86ISD::FMSUB, 0),
1654 X86_INTRINSIC_DATA(avx512_mask3_vfmsub_ps_256, FMA_OP_MASK3, X86ISD::FMSUB, 0),
1655 X86_INTRINSIC_DATA(avx512_mask3_vfmsub_ps_512, FMA_OP_MASK3, X86ISD::FMSUB,
1846 X86_INTRINSIC_DATA(fma_vfmsub_pd, INTR_TYPE_3OP, X86ISD::FMSUB, 0),
1847 X86_INTRINSIC_DATA(fma_vfmsub_pd_256, INTR_TYPE_3OP, X86ISD::FMSUB, 0),
1848 X86_INTRINSIC_DATA(fma_vfmsub_ps, INTR_TYPE_3OP, X86ISD::FMSUB, 0),
1849 X86_INTRINSIC_DATA(fma_vfmsub_ps_256, INTR_TYPE_3OP, X86ISD::FMSUB, 0),
DX86ISelLowering.h476 FMSUB, enumerator
DX86InstrFragmentsSIMD.td471 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
DX86ISelLowering.cpp22285 case X86ISD::FMSUB: return "X86ISD::FMSUB"; in getTargetNodeName()
29762 case X86ISD::FMSUB: in combineFneg()
29766 return DAG.getNode(X86ISD::FMSUB, DL, VT, Arg.getOperand(0), in combineFneg()
30229 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB; in combineFMA()
/external/llvm-project/llvm/lib/Target/X86/
DX86ISelLowering.h552 FMSUB, enumerator
DX86InstrFragmentsSIMD.td548 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFPTernaryOp, [SDNPCommutative]>;
DX86ISelLowering.cpp30962 NODE_NAME_CASE(FMSUB) in getTargetNodeName()
37348 if (FMSub.getOpcode() != X86ISD::FMSUB) in combineShuffleToFMAddSub()
37351 if (FMAdd.getOpcode() != ISD::FMA || FMSub.getOpcode() != X86ISD::FMSUB || in combineShuffleToFMAddSub()
45916 case X86ISD::FMSUB: Opcode = X86ISD::FNMSUB; break; in negateFMAOpcode()
45922 case X86ISD::FNMSUB: Opcode = X86ISD::FMSUB; break; in negateFMAOpcode()
45931 case ISD::FMA: Opcode = X86ISD::FMSUB; break; in negateFMAOpcode()
45934 case X86ISD::FMSUB: Opcode = ISD::FMA; break; in negateFMAOpcode()
45956 case X86ISD::FMSUB: Opcode = X86ISD::FNMADD; break; in negateFMAOpcode()
45958 case X86ISD::FNMADD: Opcode = X86ISD::FMSUB; break; in negateFMAOpcode()
46022 case X86ISD::FMSUB: in getNegatedExpression()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ISelLowering.h472 FMSUB, enumerator
DX86InstrFragmentsSIMD.td538 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFPTernaryOp, [SDNPCommutative]>;
DX86ISelLowering.cpp29819 case X86ISD::FMSUB: return "X86ISD::FMSUB"; in getTargetNodeName()
35007 if (FMSub.getOpcode() != X86ISD::FMSUB) in combineShuffleToFMAddSub()
35010 if (FMAdd.getOpcode() != ISD::FMA || FMSub.getOpcode() != X86ISD::FMSUB || in combineShuffleToFMAddSub()
42519 case X86ISD::FMSUB: Opcode = X86ISD::FNMSUB; break; in negateFMAOpcode()
42523 case X86ISD::FNMSUB: Opcode = X86ISD::FMSUB; break; in negateFMAOpcode()
42531 case ISD::FMA: Opcode = X86ISD::FMSUB; break; in negateFMAOpcode()
42533 case X86ISD::FMSUB: Opcode = ISD::FMA; break; in negateFMAOpcode()
42551 case X86ISD::FMSUB: Opcode = X86ISD::FNMADD; break; in negateFMAOpcode()
42553 case X86ISD::FNMADD: Opcode = X86ISD::FMSUB; break; in negateFMAOpcode()
42595 case X86ISD::FMSUB: in combineFneg()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DP9InstrResources.td413 (instregex "FMSUB(S)?$"),
/external/llvm-project/llvm/lib/Target/PowerPC/
DP9InstrResources.td414 (instregex "FMSUB(S)?$"),
DPPCInstrInfo.td3161 defm FMSUB : AForm_1r<63, 28,
3528 (FMSUB $A, $B, $C)>;
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenMCCodeEmitter.inc940 UINT64_C(4227858488), // FMSUB
3529 case PPC::FMSUB:
7350 CEFBS_None, // FMSUB = 927
DPPCGenInstrInfo.inc942 FMSUB = 927,
3911 …Commutable), 0x18ULL, ImplicitList18, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #927 = FMSUB
12651 { PPC::FMSUB_rec, PPC::FMSUB },
12851 { PPC::FMSUB, PPC::FMSUB_rec },
DPPCGenAsmWriter.inc2595 19600U, // FMSUB
4886 134U, // FMSUB
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SchedThunderX3T110.td1289 (instregex "^FMADD", "^FMSUB", "^FNMADD", "^FNMSUB")>;
DAArch64SchedThunderX2T99.td1181 (instregex "^FMADD", "^FMSUB", "^FNMADD", "^FNMSUB")>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedThunderX2T99.td1181 (instregex "^FMADD", "^FMSUB", "^FNMADD", "^FNMSUB")>;
/external/capstone/arch/PowerPC/
DPPCGenAsmWriter.inc541 18891U, // FMSUB
2063 80U, // FMSUB
4666 // FMADD, FMADDS, FMADDSo, FMADDo, FMSUB, FMSUBS, FMSUBSo, FMSUBo, FNMADD...
DPPCGenDisassemblerTables.inc2359 /* 9913 */ MCD_OPC_Decode, 137, 4, 112, // Opcode: FMSUB
/external/vixl/src/aarch64/
Ddisasm-aarch64.cc1885 FORMAT(FMSUB, "fmsub"); in VisitFPDataProcessing3Source()
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2633 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2643 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md4115 ### FMSUB ### subsection

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