Home
last modified time | relevance | path

Searched refs:FMUL_S (Results 1 – 25 of 25) sorted by relevance

/external/mesa3d/src/mesa/x86/
Dx86_xform4.S102 FMUL_S( MAT0 )
104 FMUL_S( MAT1 )
106 FMUL_S( MAT2 )
108 FMUL_S( MAT3 )
111 FMUL_S( MAT4 )
113 FMUL_S( MAT5 )
115 FMUL_S( MAT6 )
117 FMUL_S( MAT7 )
127 FMUL_S( MAT8 )
129 FMUL_S( MAT9 )
[all …]
Dx86_xform3.S102 FMUL_S( MAT0 )
104 FMUL_S( MAT1 )
106 FMUL_S( MAT2 )
108 FMUL_S( MAT3 )
111 FMUL_S( MAT4 )
113 FMUL_S( MAT5 )
115 FMUL_S( MAT6 )
117 FMUL_S( MAT7 )
127 FMUL_S( MAT8 )
129 FMUL_S( MAT9 )
[all …]
Dx86_xform2.S102 FMUL_S( MAT0 )
104 FMUL_S( MAT1 )
106 FMUL_S( MAT2 )
108 FMUL_S( MAT3 )
111 FMUL_S( MAT4 )
113 FMUL_S( MAT5 )
115 FMUL_S( MAT6 )
117 FMUL_S( MAT7 )
196 FMUL_S( MAT0 )
199 FMUL_S( MAT5 )
[all …]
Dassyntax.h749 #define FMUL_S(a) CHOICE(fmuls a, fmuls a, fmuls a) macro
1462 #define FMUL_S(a) fmul S_(a) macro
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
Dfloat_arithmetic_operations.mir92 ; FP32: [[FMUL_S:%[0-9]+]]:fgr32 = FMUL_S [[COPY]], [[COPY1]]
93 ; FP32: $f0 = COPY [[FMUL_S]]
99 ; FP64: [[FMUL_S:%[0-9]+]]:fgr32 = FMUL_S [[COPY]], [[COPY1]]
100 ; FP64: $f0 = COPY [[FMUL_S]]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoF.td139 def FMUL_S : FPALUS_rr_frm<0b0001000, "fmul.s">,
141 def : FPALUSDynFrmAlias<FMUL_S, "fmul.s">;
307 def : PatFpr32Fpr32DynFrm<fmul, FMUL_S>;
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoF.td138 def FMUL_S : FPALUS_rr_frm<0b0001000, "fmul.s">,
140 def : FPALUSDynFrmAlias<FMUL_S, "fmul.s">;
313 def : PatFpr32Fpr32DynFrm<fmul, FMUL_S>;
/external/llvm/lib/Target/Mips/
DMipsInstrFPU.td474 def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsScheduleP5600.td451 (instrs FADD_D32, FADD_D64, FADD_S, FMUL_D32, FMUL_D64, FMUL_S,
DMipsInstrFPU.td641 def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
DMipsScheduleGeneric.td811 FADD_D64, FADD_S, MADD_S, MSUB_S, FMUL_S,
/external/llvm-project/llvm/lib/Target/Mips/
DMipsScheduleP5600.td453 FMUL_PS64, FMUL_S, FSUB_D32, FSUB_D64, FSUB_PS64, FSUB_S)>;
DMipsInstrFPU.td674 def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
DMipsScheduleGeneric.td811 FADD_D64, FADD_S, MADD_S, MSUB_S, FMUL_S,
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc886 {DBGFIELD("FMUL_S") 1, false, false, 14, 2, 4, 1, 0, 0}, // #626
2570 {DBGFIELD("FMUL_S") 1, false, false, 57, 2, 4, 1, 0, 0}, // #626
DMipsGenMCCodeEmitter.inc1580 UINT64_C(1174405122), // FMUL_S
3517 case Mips::FMUL_S:
11042 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMUL_S = 1567
DMipsGenAsmWriter.inc2808 268459064U, // FMUL_S
5562 0U, // FMUL_S
DMipsGenInstrInfo.inc1582 FMUL_S = 1567,
3406 FMUL_S = 626,
6428 …MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1567 = FMUL_S
16796 { Mips::FMUL_S, Mips::FMUL_S, Mips::FMUL_S_MM },
DMipsGenFastISel.inc1577 return fastEmitInst_rr(Mips::FMUL_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
DMipsGenDisassemblerTables.inc3366 /* 2652 */ MCD::OPC_Decode, 159, 12, 207, 1, // Opcode: FMUL_S
DMipsGenAsmMatcher.inc7229 …{ 6855 /* mul.s */, Mips::FMUL_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_H…
DMipsGenGlobalISel.inc22130 …// (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S:{ *:[f32] …
22131 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_S,
DMipsGenDAGISel.inc27705 /* 52396*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMUL_S), 0,
27708 … // Dst: (FMUL_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc796 134240805U, // FMUL_S
2585 0U, // FMUL_S
DMipsGenDisassemblerTables.inc1046 /* 1829 */ MCD_OPC_Decode, 139, 6, 93, // Opcode: FMUL_S