/external/mesa3d/src/mesa/x86/ |
D | x86_xform4.S | 102 FMUL_S( MAT0 ) 104 FMUL_S( MAT1 ) 106 FMUL_S( MAT2 ) 108 FMUL_S( MAT3 ) 111 FMUL_S( MAT4 ) 113 FMUL_S( MAT5 ) 115 FMUL_S( MAT6 ) 117 FMUL_S( MAT7 ) 127 FMUL_S( MAT8 ) 129 FMUL_S( MAT9 ) [all …]
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D | x86_xform3.S | 102 FMUL_S( MAT0 ) 104 FMUL_S( MAT1 ) 106 FMUL_S( MAT2 ) 108 FMUL_S( MAT3 ) 111 FMUL_S( MAT4 ) 113 FMUL_S( MAT5 ) 115 FMUL_S( MAT6 ) 117 FMUL_S( MAT7 ) 127 FMUL_S( MAT8 ) 129 FMUL_S( MAT9 ) [all …]
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D | x86_xform2.S | 102 FMUL_S( MAT0 ) 104 FMUL_S( MAT1 ) 106 FMUL_S( MAT2 ) 108 FMUL_S( MAT3 ) 111 FMUL_S( MAT4 ) 113 FMUL_S( MAT5 ) 115 FMUL_S( MAT6 ) 117 FMUL_S( MAT7 ) 196 FMUL_S( MAT0 ) 199 FMUL_S( MAT5 ) [all …]
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D | assyntax.h | 749 #define FMUL_S(a) CHOICE(fmuls a, fmuls a, fmuls a) macro 1462 #define FMUL_S(a) fmul S_(a) macro
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/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
D | float_arithmetic_operations.mir | 92 ; FP32: [[FMUL_S:%[0-9]+]]:fgr32 = FMUL_S [[COPY]], [[COPY1]] 93 ; FP32: $f0 = COPY [[FMUL_S]] 99 ; FP64: [[FMUL_S:%[0-9]+]]:fgr32 = FMUL_S [[COPY]], [[COPY1]] 100 ; FP64: $f0 = COPY [[FMUL_S]]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
D | RISCVInstrInfoF.td | 139 def FMUL_S : FPALUS_rr_frm<0b0001000, "fmul.s">, 141 def : FPALUSDynFrmAlias<FMUL_S, "fmul.s">; 307 def : PatFpr32Fpr32DynFrm<fmul, FMUL_S>;
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/external/llvm-project/llvm/lib/Target/RISCV/ |
D | RISCVInstrInfoF.td | 138 def FMUL_S : FPALUS_rr_frm<0b0001000, "fmul.s">, 140 def : FPALUSDynFrmAlias<FMUL_S, "fmul.s">; 313 def : PatFpr32Fpr32DynFrm<fmul, FMUL_S>;
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/external/llvm/lib/Target/Mips/ |
D | MipsInstrFPU.td | 474 def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
D | MipsScheduleP5600.td | 451 (instrs FADD_D32, FADD_D64, FADD_S, FMUL_D32, FMUL_D64, FMUL_S,
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D | MipsInstrFPU.td | 641 def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
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D | MipsScheduleGeneric.td | 811 FADD_D64, FADD_S, MADD_S, MSUB_S, FMUL_S,
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/external/llvm-project/llvm/lib/Target/Mips/ |
D | MipsScheduleP5600.td | 453 FMUL_PS64, FMUL_S, FSUB_D32, FSUB_D64, FSUB_PS64, FSUB_S)>;
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D | MipsInstrFPU.td | 674 def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
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D | MipsScheduleGeneric.td | 811 FADD_D64, FADD_S, MADD_S, MSUB_S, FMUL_S,
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
D | MipsGenSubtargetInfo.inc | 886 {DBGFIELD("FMUL_S") 1, false, false, 14, 2, 4, 1, 0, 0}, // #626 2570 {DBGFIELD("FMUL_S") 1, false, false, 57, 2, 4, 1, 0, 0}, // #626
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D | MipsGenMCCodeEmitter.inc | 1580 UINT64_C(1174405122), // FMUL_S 3517 case Mips::FMUL_S: 11042 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMUL_S = 1567
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D | MipsGenAsmWriter.inc | 2808 268459064U, // FMUL_S 5562 0U, // FMUL_S
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D | MipsGenInstrInfo.inc | 1582 FMUL_S = 1567, 3406 FMUL_S = 626, 6428 …MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1567 = FMUL_S 16796 { Mips::FMUL_S, Mips::FMUL_S, Mips::FMUL_S_MM },
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D | MipsGenFastISel.inc | 1577 return fastEmitInst_rr(Mips::FMUL_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
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D | MipsGenDisassemblerTables.inc | 3366 /* 2652 */ MCD::OPC_Decode, 159, 12, 207, 1, // Opcode: FMUL_S
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D | MipsGenAsmMatcher.inc | 7229 …{ 6855 /* mul.s */, Mips::FMUL_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_H…
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D | MipsGenGlobalISel.inc | 22130 …// (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S:{ *:[f32] … 22131 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_S,
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D | MipsGenDAGISel.inc | 27705 /* 52396*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMUL_S), 0, 27708 … // Dst: (FMUL_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
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/external/capstone/arch/Mips/ |
D | MipsGenAsmWriter.inc | 796 134240805U, // FMUL_S 2585 0U, // FMUL_S
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D | MipsGenDisassemblerTables.inc | 1046 /* 1829 */ MCD_OPC_Decode, 139, 6, 93, // Opcode: FMUL_S
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