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Searched refs:FNEG (Results 1 – 25 of 164) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-fneg.mir14 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
15 ; SI: $vgpr0 = COPY [[FNEG]](s32)
18 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
19 ; VI: $vgpr0 = COPY [[FNEG]](s32)
22 ; GFX9: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
23 ; GFX9: $vgpr0 = COPY [[FNEG]](s32)
36 ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY]]
37 ; SI: $vgpr0_vgpr1 = COPY [[FNEG]](s64)
40 ; VI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY]]
41 ; VI: $vgpr0_vgpr1 = COPY [[FNEG]](s64)
[all …]
Dregbankselect-fneg.mir14 ; CHECK: [[FNEG:%[0-9]+]]:sgpr(s32) = G_FNEG [[COPY]]
15 ; CHECK: $vgpr0 = COPY [[FNEG]](s32)
30 ; CHECK: [[FNEG:%[0-9]+]]:vgpr(s32) = G_FNEG [[COPY]]
31 ; CHECK: $vgpr0 = COPY [[FNEG]](s32)
Dlegalize-fdiv.mir32 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]]
33 ; SI: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[FNEG]], [[INT4]], [[C]]
36 ; SI: [[FMA2:%[0-9]+]]:_(s32) = G_FMA [[FNEG]], [[FMUL]], [[INT2]]
38 ; SI: [[FMA4:%[0-9]+]]:_(s32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
121 ; SI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]]
122 ; SI: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[FNEG]], [[INT4]], [[C]]
125 ; SI: [[FMA2:%[0-9]+]]:_(s32) = G_FMA [[FNEG]], [[FMUL]], [[INT2]]
127 ; SI: [[FMA4:%[0-9]+]]:_(s32) = G_FMA [[FNEG]], [[FMA3]], [[INT2]]
138 ; VI: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]]
139 ; VI: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[FNEG]], [[INT4]], [[C]]
[all …]
Dlegalize-fsub.mir41 ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
42 ; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[FNEG]]
47 ; VI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
48 ; VI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[FNEG]]
53 ; GFX9: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
54 ; GFX9: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[FNEG]]
71 ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
72 ; SI: [[FADD:%[0-9]+]]:_(s64) = nnan nsz G_FADD [[COPY]], [[FNEG]]
77 ; VI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
78 ; VI: [[FADD:%[0-9]+]]:_(s64) = nnan nsz G_FADD [[COPY]], [[FNEG]]
[all …]
Dinst-select-fneg.mir58 ; GCN: [[FNEG:%[0-9]+]]:vgpr_32(s32) = G_FNEG [[COPY]]
59 ; GCN: $vgpr0 = COPY [[FNEG]](s32)
123 ; GCN: [[FNEG:%[0-9]+]]:vgpr_32(s16) = G_FNEG [[TRUNC]]
124 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FNEG]](s16)
185 ; GCN: [[FNEG:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FNEG [[COPY]]
186 ; GCN: $vgpr0 = COPY [[FNEG]](<2 x s16>)
250 ; GCN: [[FNEG:%[0-9]+]]:vgpr(s64) = G_FNEG [[COPY]]
251 ; GCN: S_ENDPGM 0, implicit [[FNEG]](s64)
383 ; GCN: [[FNEG:%[0-9]+]]:sgpr(s16) = G_FNEG [[TRUNC]]
384 ; GCN: [[FNEG1:%[0-9]+]]:vgpr_32(s16) = G_FNEG [[FNEG]]
Dlegalize-intrinsic-round.mir146 ; GFX6: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[SELECT1]]
147 ; GFX6: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[FNEG]]
162 ; GFX8: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INTRINSIC_TRUNC]]
163 ; GFX8: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[FNEG]]
178 ; GFX9: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INTRINSIC_TRUNC]]
179 ; GFX9: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[FNEG]]
311 ; GFX6: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[SELECT1]]
312 ; GFX6: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[UV]], [[FNEG]]
349 ; GFX8: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INTRINSIC_TRUNC]]
350 ; GFX8: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[UV]], [[FNEG]]
[all …]
Dlegalize-frint.mir64 ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[OR]]
65 ; SI: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[FADD]], [[FNEG]]
136 ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[OR]]
137 ; SI: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[FADD]], [[FNEG]]
Dinst-select-fmul.v2s16.mir60 ; GFX9: [[FNEG:%[0-9]+]]:vgpr(s16) = G_FNEG [[TRUNC]]
61 ; GFX9: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FNEG]](s16)
Dinst-select-ffloor.s16.mir86 ; SI: [[FNEG:%[0-9]+]]:vgpr(s16) = G_FNEG [[TRUNC]]
87 ; SI: [[FFLOOR:%[0-9]+]]:vgpr(s16) = G_FFLOOR [[FNEG]]
Dlegalize-sitofp.mir135 ; GFX6: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[ADD]]
137 ; GFX6: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[FNEG]], [[ADD]]
175 ; GFX8: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[ADD]]
177 ; GFX8: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[FNEG]], [[ADD]]
487 ; GFX6: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[ADD]]
489 ; GFX6: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[FNEG]], [[ADD]]
529 ; GFX8: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[ADD]]
531 ; GFX8: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[FNEG]], [[ADD]]
581 ; GFX6: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[ADD]]
583 ; GFX6: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[FNEG]], [[ADD]]
[all …]
Dlegalize-ffloor.mir42 ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[SELECT]]
43 ; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[FNEG]]
70 ; SI: [[FNEG:%[0-9]+]]:_(s64) = nnan G_FNEG [[FMINNUM_IEEE]]
71 ; SI: [[FADD:%[0-9]+]]:_(s64) = nnan G_FADD [[COPY]], [[FNEG]]
100 ; SI: [[FNEG:%[0-9]+]]:_(s64) = nsz G_FNEG [[SELECT]]
101 ; SI: [[FADD:%[0-9]+]]:_(s64) = nsz G_FADD [[COPY]], [[FNEG]]
231 ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[SELECT]]
232 ; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[UV]], [[FNEG]]
/external/apache-commons-bcel/src/main/java/org/apache/bcel/generic/
DFNEG.java26 public class FNEG extends ArithmeticInstruction { class
28 public FNEG() { in FNEG() method in FNEG
29 super(org.apache.bcel.Const.FNEG); in FNEG()
DInstructionConst.java110 public static final ArithmeticInstruction FNEG = new FNEG(); field in InstructionConst
241 INSTRUCTIONS[Const.FNEG] = FNEG;
DInstructionConstants.java111 ArithmeticInstruction FNEG = new FNEG(); field
246 INSTRUCTIONS[Const.FNEG] = FNEG; in Clinit()
DArithmeticInstruction.java62 case Const.FNEG: in getType()
/external/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/
Dreduction2.ll89 ; CHECK-NEXT: [[FNEG:%.*]] = fneg double [[B:%.*]]
91 ; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> undef, double [[FNEG]], i32 0
138 ; CHECK-NEXT: [[FNEG:%.*]] = fneg double [[B:%.*]]
140 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double [[FNEG]], i32 0
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp426 setOperationAction(ISD::FNEG, VT, Expand); in AMDGPUTargetLowering()
499 setTargetDAGCombine(ISD::FNEG); in AMDGPUTargetLowering()
1585 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq); in LowerDIVREM24()
2477 SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R); in LowerINT_TO_FP32()
3523 (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) { in foldFreeOpFromSelect()
3529 if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) { in foldFreeOpFromSelect()
3536 if ((LHS.getOpcode() == ISD::FNEG || LHS.getOpcode() == ISD::FABS) && CRHS) { in foldFreeOpFromSelect()
3548 if (LHS.getOpcode() == ISD::FNEG && fnegFoldsIntoOp(Opc)) in foldFreeOpFromSelect()
3555 if (LHS.getOpcode() == ISD::FNEG) in foldFreeOpFromSelect()
3556 NewRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in foldFreeOpFromSelect()
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dlegalize-fp-arith.mir54 ; CHECK: [[FNEG:%[0-9]+]]:_(<2 x s32>) = G_FNEG [[COPY]]
55 ; CHECK: $d0 = COPY [[FNEG]](<2 x s32>)
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp492 setOperationAction(ISD::FNEG, VT, Expand); in AMDGPUTargetLowering()
569 setTargetDAGCombine(ISD::FNEG); in AMDGPUTargetLowering()
1710 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq); in LowerDIVREM24()
2102 SDValue Neg = DAG.getNode(ISD::FNEG, SL, VT, Trunc, Flags); in LowerFREM()
2475 SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R); in LowerINT_TO_FP32()
3502 (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) { in foldFreeOpFromSelect()
3508 if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) { in foldFreeOpFromSelect()
3515 if ((LHS.getOpcode() == ISD::FNEG || LHS.getOpcode() == ISD::FABS) && CRHS) { in foldFreeOpFromSelect()
3527 if (LHS.getOpcode() == ISD::FNEG && fnegFoldsIntoOp(Opc)) in foldFreeOpFromSelect()
3534 if (LHS.getOpcode() == ISD::FNEG) in foldFreeOpFromSelect()
[all …]
/external/javassist/src/main/javassist/bytecode/
DOpcode.java103 int FNEG = 118; field
/external/llvm-project/llvm/test/CodeGen/ARM/
Dlegalize-fneg.ll7 ; Check Y = FNEG(X) -> Y = X ^ sign mask and no lib call is generated.
/external/llvm/test/CodeGen/X86/
Dfnabs.ll4 ; FNABS(x) operation -> FNEG (FABS(x)).
/external/llvm-project/llvm/test/CodeGen/X86/
Dfnabs.ll4 ; FNABS(x) operation -> FNEG (FABS(x)).
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h524 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
/external/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp1010 if ((Opc == ISD::FABS || Opc == ISD::FNEG) && !HST->hasV5TOps()) { in SelectBitOp()
1016 if (Opc != ISD::FABS && Opc != ISD::FNEG) { in SelectBitOp()
1053 if (Opc != ISD::FABS && Opc != ISD::FNEG) { in SelectBitOp()
1080 case ISD::FNEG: in SelectBitOp()
1124 if (Opc != ISD::FABS && Opc != ISD::FNEG) in SelectBitOp()
1232 case ISD::FNEG: in Select()

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